ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 52

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.7
5.8
5.9
5.10
5.11
8291A–AVR–10/11
Double Buffering
Transfer Buffers
Error detection
Software Reset
Protection
one or more channels should have a fixed priority or if a round robin scheme should be used. A
round robin scheme means that the channel that last transferred data will have the lowest
priority.
To allow for continuous transfer, the two channels can be interlinked so that the second takes
over the transfer when the first is finished, and vice versa. This leaves time for the application to
process the data transferred by the first channel, prepare fresh data buffers, and set up the
channel registers again while the second channel is working. This is referred to as double buffer-
ing or chained transfers.
When double buffering is enabled for a channel pair, it is important that the two channels are
configured with the same repeat count. The block sizes need not be equal, but for most applica-
tions they should be, along with the rest of the channel’s operation mode settings.
To avoid unnecessary bus loading when doing data transfer between memories with different
access timing (for example, I/O register and external memory), the DMA controller has a four-
byte buffer. Two bytes will be read from the source address and written to this buffer before a
write to the destination is started.
The DMA controller can detect erroneous operation. Error conditions are detected individually
for each DMA channel, and the error conditions are:
Both the DMA controller and a DMA channel can be reset from the user software. When the
DMA controller is reset, all registers associated with the DMA controller, including channels, are
cleared. A software reset can be done only when the DMA controller is disabled.
When a DMA channel is reset, all registers associated with the DMA channel are cleared. A soft-
ware reset can be done only when the DMA channel is disabled.
In order to ensure safe operation, some of the channel registers are protected during a transac-
tion. When the DMA channel busy flag (CHnBUSY) is set for a channel, the user can modify only
the following registers and bits:
• Write to memory mapped EEPROM locations
• Reading EEPROM when the EEPROM is off (sleep entered)
• DMA controller or a busy channel is disabled in software during a transfer
• CTRL register
• INTFLAGS register
• TEMP registers
• CHEN, CHRST, TRFREQ, and REPEAT bits of the channel CTRL register
• TRIGSRC register
Atmel AVR XMEGA B
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