ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 73

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.8.2
8291A–AVR–10/11
CHnCTRL – Channel n Control Register
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 6:5 – QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals, where a valid
index signal is recognized and the counter index data event is given according to
page
nal is used.These bits are available only for CH0CTRL.
Table 6-5.
• Bit 4 – QDIEN: Quadrature Decode Index Enable
When this bit is set, the event channel will be used as a QDEC index source, and the index data
event will be enabled.
This bit is available only for CH0CTRL.
• Bit 3 – QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation.
This bit is available only for CH0CTRL.
• Bit 2:0 – DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event
channel only when the event source has been active and sampled with the same level for the
number of peripheral clock cycles defined by DIGFILT.
Table 6-6.
Bit
Read/Write
Initial Value
QDIRM[1:0]
0
0
1
1
73. These bits should only be set when a quadrature encoder with a connected index sig-
DIGFILT[2:0]
0
1
0
1
000
001
010
011
100
QDIRM bit settings.
Digital filter coefficient values .
7
–
R
0
Index Recognition State
{QDPH0, QDPH90} = 0b00
{QDPH0, QDPH90} = 0b01
{QDPH0, QDPH90} = 0b10
{QDPH0, QDPH90} = 0b11
R/W
6
0
Group Configuration
1SAMPLE
2SAMPLES
3SAMPLES
4SAMPLES
5SAMPLES
QDIRM[1:0]
R/W
5
0
QDIEN
R/W
4
0
Description
One sample
Two samples
Three samples
Four samples
Five samples
QDEN
R/W
3
0
Atmel AVR XMEGA B
R/W
2
0
DIGFILT[2:0]
R/W
1
0
R/W
0
0
Table 6-5 on
CHnCTRL
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