SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 1025
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- Current page: 1025 of 1183
- Download datasheet (26Mb)
40.3.2
40.3.3
40.3.3.1
40.3.3.2
6430E–ATARM–29-Aug-11
Memory Peripherals
Handshaking Interface
Software Handshaking
Chunk Transactions
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting
hmastlock for the duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel
locking is asserted for the duration of bus locking at a minimum.
Figure 40-3 on page 1023
peripheral. There is no handshaking interface with the DMAC, and therefore the memory periph-
eral can never be a flow controller. Once the channel is enabled, the transfer proceeds
immediately without waiting for a transaction request. The alternative to not having a transac-
tion-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the
peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA trans-
fers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16
wait states be inserted onto the bus. By using the handshaking interface, the peripheral can sig-
nal to the DMAC that it is ready to transmit/receive data, and then the DMAC can access the
peripheral without the peripheral inserting wait states onto the bus.
Handshaking interfaces are used at the transaction level to control the flow of single or chunk
transfers. The operation of the handshaking interface is different and depends on whether the
peripheral or the DMAC is the flow controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to trans-
fer/accept data over the AMBA bus. A non-memory peripheral can request a DMAC transfer
through the DMAC using one of two handshaking interfaces:
Software selects between the hardware or software handshaking interface on a per-channel
basis. Software handshaking is accomplished through memory-mapped registers, while hard-
ware handshaking is accomplished using a dedicated handshaking interface.
When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates
this request by sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMAC
transaction. These software registers are used to implement the software handshaking
interface.
The SRC_H2SEL/DST_H2SEL bit in the DMAC_CFGx channel configuration register must be
set to zero to enable software handshaking.
When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is
not used, and the values in these registers are ignored.
Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x
is the channel number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk
transfer request, where x is the channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[2x] or
DMAC_CREQ[2x+1].
• Hardware handshaking
• Software handshaking
shows the DMAC transfer hierarchy of the DMAC for a memory
SAM3U Series
1025
Related parts for SAM3U4E
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![U641B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
![U4082B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
![U4089B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
![U4255BM-M](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
![U4089B-P](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
![TDA4470](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
![ATF22V10B-25PC](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
![AT89C51ED2-IM](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
![AT24C01](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet:
![U6046B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
U6046BREAR WINDOW HEATING TIMER / LONG-TERM TIMER
Manufacturer:
ATMEL Corporation
Datasheet: