SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 342
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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24.4.3
24.5
342
Write Protect Registers
SAM3U Series
Fixed Priority Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixed priority defined by the user. If two or more master’s requests
are active at the same time, the master with the highest priority number is serviced first. If two or
more master’s requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (MATRIX_PRAS and MATRIX_PRBS).
To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX
address space from address offset 0x000 to 0x1FC can be write-protected by setting the WPEN
bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR).
If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC
is detected, then the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR)
is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR)
with the appropriate access key WPKEY.
The protected registers are:
“Bus Matrix Master Configuration Registers”
“Bus Matrix Slave Configuration Registers”
“Bus Matrix Priority Registers For Slaves”
“Bus Matrix Master Remap Control Register”
“Bus Matrix Master Remap Control Register”
6430E–ATARM–29-Aug-11
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