SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 362
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Figure 25-8. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
25.10.2.2
Figure 25-9. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
362
362
SAM3U Series
SAM3U Series
Read is Controlled by NCS (READ_MODE = 0)
NBS0,NBS1,
A0, A1
NBS0,NBS1,
A0, A1
D[15:0]
D[15:0]
A[23:2]
A[23:2]
MCK
MCK
NRD
NRD
NCS
NCS
Figure 25-9
NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is
raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC
internally samples the data on the rising edge of Master Clock that generates the rising edge of
NCS, whatever the programmed waveform of NRD may be.
shows the typical read cycle. The read data is valid t
t
t
PACC
PACC
Data Sampling
Data Sampling
PACC
after the falling edge of the
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
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