SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 210
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.22 Memory protection unit
210
SAM3U Series
This section describes the Memory protection unit (MPU).
The MPU divides the memory map into a number of regions, and defines the location, size,
access permissions, and memory attributes of each region. It supports:
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3
MPU defines:
When memory regions overlap, a memory access is affected by the attributes of the region with
the highest number. For example, the attributes for region 7 take precedence over the attributes
of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but
is accessible from privileged software only.
The Cortex-M3 MPU memory map is unified. This means instruction accesses and data
accesses have same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault. This causes a fault exception, and might cause termination of the
process in an OS environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the
process to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types, see
butes” on page
Table 13-34
behavior attributes that are not relevant to most microcontroller implementations. See
configuration for a microcontroller” on page 223
implementation.
Table 13-34. Memory attributes summary
Memory
type
Strongly-
ordered
Device
• independent attribute settings for each region
• overlapping regions
• export of memory attributes to the system.
• eight separate memory regions, 0-7
• a background region.
Shareability
-
Shared
shows the possible MPU region attributes. These include Share ability and cache
68.
Other attributes
-
-
Description
All accesses to Strongly-ordered memory occur
in program order. All Strongly-ordered regions
are assumed to be shared.
Memory-mapped peripherals that several
processors share.
for guidelines for programming such an
“Memory regions, types and attri-
6430E–ATARM–29-Aug-11
“MPU
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