SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 432
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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25.18.20 SMC Timings Register
Name:
Address:
Access:
Reset:
• TCLR: CLE to REN Low Delay
Command Latch Enable falling edge to Read Enable falling edge timing.
Latch Enable Falling to Read Enable Falling = (TCLR[3] * 64) + TCLR[2:0] clock cycles.
• TADL: ALE to Data Start
Last address latch cycle to the first rising edge of WEN for data input.
Last address latch to first rising edge of WEN = (TADL[3] * 64) + TADL[2:0] clock cycles.
• TAR: ALE to REN Low Delay
Address Latch Enable falling edge to Read Enable falling edge timing.
Address Latch Enable to Read Enable = (TAR[3] * 64) + TAR[2:0] clock cycles.
• OCMS: Off Chip Memory Scrambling Enable
When set to one, the memory scrambling is activated.
• TRR: Ready to REN Low Delay
Ready/Busy signal to Read Enable falling edge timing.
Read to REN = (TRR[3] * 64) + TRR[2:0] clock cycles.
• TWB: WEN High to REN to Busy
Write Enable rising edge to Ready/Busy falling edge timing.
Write Enable to Read/Busy = (TWB[3] * 64) + TWB[2:0] clock cycles.
• RBNSEL: Ready/Busy Line Selection
This field indicates the selected Ready/Busy Line from the RBN bundle.
• NFSEL: NAND Flash Selection
If this bit is set to one, the chip select is assigned to NAND Flash write enable and read enable lines drive the Error Correct-
ing Code module.
432
432
NFSEL
31
23
15
–
–
7
SAM3U Series
SAM3U Series
0x400E007C [0], 0x400E0090 [1], 0x400E00A4 [2], 0x400E00B8 [3]
SMC_TIMINGSx [x=0..3]
Read-write
0x00000000
30
22
14
–
–
6
TADL
RBNSEL
29
21
13
–
–
5
OCMS
28
20
12
–
4
27
19
11
3
26
18
10
2
TCLR
TWB
TRR
TAR
25
17
9
1
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
24
16
8
0
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