SAM7X128 Atmel Corporation, SAM7X128 Datasheet - Page 106

• Manufacturer Part Number: SAM7X128
• Manufacturer: Atmel Corporation

Specifications of SAM7X128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3
Note:
19.2.3
19.2.4
106
ARM Request (16-bit)
Buffer (32 bits)
Data To ARM
Flash Access
Master Clock
When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the
third access FWS cycles, the fourth access one cycle, etc.
Code Fetch
SAM7X512/256/128
Write Operations
Flash Commands
@Byte 0
3 Wait State Cycles
The internal memory area reserved for the embedded Flash can also be written through a write-
only latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap
around within the internal memory area address space and appear to be repeated 1024 times
within it.
Write operations can be prevented by programming the Memory Protection Unit of the product.
Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in the number of wait states equal to the number of wait states
for read operations + 1, except for FWS = 3 (see
The EFC offers a command set to manage programming the memory flash, locking and unlock-
ing lock sectors, consecutive programming and locking, and full Flash erasing.
Table 19-2.
Command
Write page
Set Lock Bit
Write Page and Lock
Clear Lock Bit
Erase all
Set General-purpose NVM Bit
Clear General-purpose NVM Bit
Set Security Bit
Bytes 0-3
Set of Commands
@2
0-1
3 Wait State Cycles
@4
2-3
Bytes 0-3
Bytes 4-7
@6
4-5
3 Wait State Cycles
@8
6-7
“MC Flash Mode Register” on page
Bytes 8-11
Bytes 4-7
Value
0x0B
0x0D
0x0F
0x01
0x02
0x03
0x04
0x08
@10
8-9 10-11
3 Wait State Cycles
@12
Mnemonic
WP
SLB
WPL
CLB
EA
SGPB
CGPB
SSB
Bytes 12-15
6120I–ATARM–06-Apr-11
Bytes 8-11
114).
12-13