SAM7X128 Atmel Corporation, SAM7X128 Datasheet - Page 663
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SAM7X128
Manufacturer Part Number
SAM7X128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7X128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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41.5.9.3
41.5.9.4
41.5.9.5
41.5.10
41.5.10.1
41.5.10.2
41.5.10.3
6120I–ATARM–06-Apr-11
Universal Synchronous Asynchronous Receiver Transmitter (USART)
USART: CTS in Hardware Handshaking
USART: Hardware Handshaking – Two Characters Sent
USART: RXBRK Flag Error in Asynchronous Mode
TWI: NACK Status Bit Lost
TWI: Possible Receive Holding Register Corruption
TWI: Software Reset
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection
and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set.
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as
long as transmission is not completed.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of
the TWI_SR.
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the
TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor
OVERRUN status bits are set if this occurs.
The user must be sure that received data is read before transmitting any new data.
when a software reset is performed during a frame and when TWCK is low, it is impossible to ini-
tiate a new transfer in READ or WRITE mode.
None.
When Hardware Handshaking is used and if CTS goes low near the end of the start bit, a char-
acter can be lost.
CTS must not go high during a time slot occurring between 2 Master Clock periods before and
16 Master Clock periods after the rising edge of the start bit.
None.
If CTS switches from 0 to 1 during the TX of a character and if the holding register (US_THR) is
not empty, the content of US_THR will also be transmitted.
Don't use the PDC in transmit mode and do not fill US_THR before TXEMPTY is set at 1.
In receiver mode, when there are two consecutive characters (without time guard in between),
RXBRK is not taken into account. As a result, the RXBRK flag is not enabled correctly and the
frame error flag is set
Constraints on the transmitter device connected to the SAM7X USART receiver side:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SAM7X512/256/128
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