SAM7X128 Atmel Corporation, SAM7X128 Datasheet - Page 649

• Manufacturer Part Number: SAM7X128
• Manufacturer: Atmel Corporation

Specifications of SAM7X128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.4.2
41.4.2.1
41.4.2.2
41.4.3
41.4.3.1
41.4.4
41.4.4.1
41.4.4.2
41.4.5
41.4.5.1
6120I–ATARM–06-Apr-11
Controller Area Network (CAN)
Embedded Flash Controller (EFC)
Ethernet MAC (EMAC)
Peripheral Input/Output (PIO)
CAN: Low Power Mode and Error Frame
CAN: Low Power Mode and Pending Transmit Messages
EFC: Embedded Flash Access Time
EMAC: Possible Event Loss when Reading EMAC_ISR
EMAC: Possible Event Loss when Reading the Statistics Register Block
PIO: Leakage on PB27 - PB30
If the Low Power Mode is activated while the CAN is generating an error frame, this error frame
may be shortened.
None
No pending transmit messages may be sent once the CAN Controller enters Low-power Mode.
Check that all messages have been sent by reading the related Flags before entering Low-
power Mode.
The embedded Flash maximum access time is 25 MHz (instead of 30 MHz at zero Wait State
(FWS = 0). The maximum operating frequency with one Wait State (FWS = 1) is still 55 MHz.
Set one wait state (FWS = 1) if the frequency is above 25 MHz.
If an event occurs within the same clock cycle in which the EMAC_ISR is read, the correspond-
ing bit might be cleared even though it has not been read at 1. This might lead to the loss of this
event.
Each time the software reads EMAC_ISR, it has to check the contents of the Transmit Status
Register (EMAC_TSR), the Receive Status Register (EMAC_RSR) and the Network Status
Register (EMAC_NSR), as the possible lost event is still notified in one of these registers.
If an event occurs within the same clock cycle during which a statistics register is read, the cor-
responding counter might lose this event. This might lead to the loss of the incrementation of
one for this counter.
None
When PB27, PB28, PB29 or PB30 (the I/O lines multiplexed with the analog inputs) are set as
digital inputs with pull-up disabled, the leakage can be 25 µA in worst case and 90 nA in typical
case per I/O when the I/O is set externally at low level.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SAM7X512/256/128
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