SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 141

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22. Peripheral DMA Controller (PDC)
22.1
22.2
6120I–ATARM–06-Apr-11
Overview
Block Diagram
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as
the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral
DMA Controller avoids processor intervention and removes the processor interrupt-handling
overhead. This significantly reduces the number of clock cycles required for a data transfer and,
as a result, improves the performance of the microcontroller and makes it more power efficient.
The PDC channels are implemented in pairs, each pair being dedicated to a particular periph-
eral. One channel in the pair is dedicated to the receiving channel and one to the transmitting
channel of each UART, USART, SSC and SPI.
The user interface of a PDC channel is integrated in the memory space of each peripheral. It
contains:
The peripheral triggers PDC transfers using transmit and receive signals. When the pro-
grammed data is transferred, an end of transfer interrupt is generated by the corresponding
peripheral.
Figure 22-1. Block Diagram
• A 32-bit memory pointer register
• A 16-bit transfer count register
• A 32-bit register for next memory pointer
• A 16-bit register for next transfer count
Peripheral
Control
THR
RHR
Status & Control
PDC Channel 0
PDC Channel 1
Peripheral DMA Controller
SAM7X512/256/128
Control
Controller
Memory
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