SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 514

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

36.6.4.5
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SAM7X512/256/128
Fault Confinement
To distinguish between temporary and permanent failures, every CAN controller has two error
counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The two counters
are incremented upon detected errors and are decremented upon correct transmissions or
receptions, respectively. Depending on the counter values, the state of the node changes: the
initial state of the CAN controller is Error Active, meaning that the controller can send Error
Active flags. The controller changes to the Error Passive state if there is an accumulation of
errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state
transition to Bus Off.
Figure 36-7. Line Error Mode
An error active unit takes part in bus communication and sends an active error frame when the
CAN controller detects an error.
An error passive unit cannot send an active error frame. It takes part in bus communication, but
when an error is detected, a passive error frame is sent. Also, after a transmission, an error pas-
sive unit waits before initiating further transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two errors counters (TEC and REC) are implemented. These counters are
accessible via the CAN_ECR register. The state of the CAN controller is automatically updated
according to these counter values. If the CAN controller is in Error Active state, then the ERRA
bit is set in the CAN_SR register. The corresponding interrupt is pending while the interrupt is
not masked in the CAN_IMR register. If the CAN controller is in Error Passive Mode, then the
ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is
set in the CAN_IMR register. If the CAN is in Bus Off Mode, then the BOFF bit is set in the
CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in
the CAN_IMR register.
• Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the
Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a
dominant bit. If this is the case, at least one other node has received the frame correctly. If
not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an
Error Frame transmission.
REC < 127
TEC < 127
and
PASSIVE
ERROR
ERROR
ACTIVE
TEC > 255
Init
REC > 127
TEC >127
or
128 occurences of 11 consecutive recessive bits
BUS OFF
CAN controller reset
6120I–ATARM–06-Apr-11
or