SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 96

no-image

SAM7X256

Manufacturer Part Number
SAM7X256
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7X256

Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
18.3.4
18.3.5
18.3.6
96
SAM7X512/256/128
Abort Status
Embedded Flash Controller
Misalignment Detector
There are two reasons for an abort to occur:
When an abort occurs, a signal is sent back to all the masters, regardless of which one has gen-
erated the access. However, only the ARM7TDMI can take an abort signal into account, and
only under the condition that it was generating an access. The Peripheral DMA Controller and
the EMAC do not handle the abort input signal. Note that the connections are not represented in
Figure
To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates
an Abort Status register set.
The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in
MC_ASR and include:
In the case of a Data Abort from the processor, the address of the data access is stored. This is
useful, as searching for which address generated the abort would require disassembling the
instructions and full knowledge of the processor context.
In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipe-
lined in the ARM processor. The ARM processor takes the prefetch abort into account only if the
read instruction is executed and it is probable that several aborts have occurred during this time.
Thus, in this case, it is preferable to use the content of the Abort Link register of the ARM
processor.
The Embedded Flash Controller is added to the Memory Controller and ensures the interface of
the flash block with the 32-bit internal bus. It allows an increase of performance in Thumb Mode
for Code Fetch with its system of 32-bit buffers. It also manages with the programming, erasing,
locking and unlocking sequences thanks to a full set of commands.
The Memory Controller features a Misalignment Detector that checks the consistency of the
accesses.
For each access, regardless of the master, the size of the access and the bits 0 and 1 of the
address bus are checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0,
or if the type of the access is a half-word (16-bit) and the bit 0 is not 0, an abort is returned to the
master and the access is cancelled. Note that the accesses of the ARM processor when it is
fetching instructions are not checked.
• access to an undefined address
• an access to a misaligned address.
• the size of the request (field ABTSZ)
• the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)
• whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned
• the source of the access leading to the last abort (bits MST_EMAC, MST_PDC and
• whether or not an abort occurred for each master since the last read of the register (bits
address (bit MISADD)
MST_ARM)
SVMST_EMAC, SVMST_PDC and SVMST_ARM) unless this information is loaded in MST
bits
18-1.
6120I–ATARM–06-Apr-11

Related parts for SAM7X256