SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 60

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SAM7X256

Manufacturer Part Number
SAM7X256
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7X256

Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
13.2.4
13.2.4.1
Figure 13-4. Power-up Reset
60
SAM7X512/256/128
periph_nreset
Reset States
Main Supply
POR output
proc_nreset
(nrst_out)
Power-up Reset
SLCK
NRST
MCK
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up
counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow
Clock oscillator is stable before starting up the device.
The startup time, as shown in
startup time. After the startup time, the reset signals are released and the field RSTTYP in
RSTC_SR reports a Power-up Reset.
When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted
immediately.
Startup Time
Figure
Processor Startup
EXTERNAL RESET LENGTH
= 3 cycles
13-4, is hardcoded to comply with the Slow Clock Oscillator
= 2 cycles
Freq.
Any
6120I–ATARM–06-Apr-11

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