SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 427
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 427 of 1145
- Download datasheet (26Mb)
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
An additional 200 cycles of clock are required for locking DLL
8. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The applica-
9. Program DLL field into the Configuration Register (see
10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set
11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
13. Program DLL field into the Configuration Register (see
14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-
15. Program OCD field into the Configuration Register (see
16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The
17. Program OCD field into the Configuration Register (see
18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The
tion must set Mode to 5 in the Mode Register (see
perform a write access to the DDR2-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example,
with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the
DDR2-SDRAM write access should be done at the address 0x20400000.
high (Enable DLL reset).
Mode to 3 in the Mode Register (see
access to the DDR2-SDRAM to acknowledge this command. The write address must
be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should
be done at the address 0x20000000.
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
SDRAM address to acknowledge this command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see
tion twice to acknowledge these commands.
low (Disable DLL reset).
SDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The
application must set Mode to 3 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit
128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write
access should be done at the address 0x20000000
high (OCD calibration default).
application must set Mode to 5 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20400000.
low (OCD calibration mode exit).
application must set Mode to 5 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20400000.
Section 30.7.1 on page
Section 30.7.1 on page
452). Performs a write access to any DDR2-SDRAM loca-
Section 30.7.1 on page
452). Perform a write access to any DDR2-
Section 30.7.1 on page
Section 30.7.3 on page
Section 30.7.3 on page
Section 30.7.3 on page
Section 30.7.3 on page
Section 30.7.1 on page
Section 30.7.1 on page
Section 30.7.1 on page
452) and perform a write
SAM9X25
SAM9X25
452) and
454) to
454) to
454) to
454) to
452)
452)
452)
427
427
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