SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 673
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 673 of 1145
- Download datasheet (26Mb)
35.7.3.6
35.7.3.7
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
SPI Direct Access Memory Controller (DMAC)
Peripheral Chip Select Decoding
In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to
reduce processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC
is an optimal means, as the size of the data transfer between the memory and the SPI is either 8
bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be
reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro-
gramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data
to be transmitted and the peripheral it is destined to. Using the DMAC in this mode requires 32-
bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, how-
ever the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI
lines with the chip select configuration registers. This is not the optimal means in term of mem-
ory size for the buffers, but it provides a very effective means to exchange data with several
peripherals without any intervention of the processor.
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip
Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by
writing the PCSDEC bit at 1 in the Mode Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line
is activated, i.e., one NPCS line driven low at a time. If two bits are defined low in a PCS field,
only the lowest numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on
NPCS lines of either the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when
not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0
defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the
PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on
the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
an implementation.
If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line
must be disabled. This is not needed for all other chip select lines since Mode Fault Detection is
only on NPCS0.
Figure 35-9
below shows such
SAM9X25
SAM9X25
673
673
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