SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 470
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 470 of 1145
- Download datasheet (26Mb)
31.2.1
470
470
SAM9X25
SAM9X25
DMA Controller 0
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals listed below. The hardware interface numbers are also given in
Table
Table 31-1.
Instance Name
HSMCI0
SPI0
SPI0
USART0
USART0
USART1
USART1
TWI0
• Channel Buffering
• Channel Control
• Transfer Initiation
• Interrupt
• Two Masters
• Embeds 8 channels
• 64-byte FIFO for channel 0, 16-byte FIFO for Channels 1 to 7
• Features:
– Unaligned system address to data transfer width supported in hardware
– Picture-In-Picture Mode (on DMAC0 only)
– 16-word FIFO (64-word for channel 0 of DMAC0)
– Automatic packing/unpacking of data to fit FIFO width
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
– Suspend DMA operation
– Programmable DMA lock transfer support
– Support for Software handshaking interface. Memory mapped registers can be used
– Programmable Interrupt generation on DMA Transfer completion Block Transfer
– Linked List support with Status Write Back operation at End of Transfer
– Word, HalfWord, Byte transfer support.
– Memory to Memory transfer
– Peripheral to memory
– Memory to peripheral
31-1.
to control the flow of a DMA transfer in place of a hardware handshaking interface
completion, Single/Multiple transaction completion or Error condition
DMA Channel Definition
T/R
RX/TX
TX
RX
TX
RX
TX
RX
TX
DMA Channel HW
interface Number
0
1
2
3
4
5
6
7
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
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