SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 62
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 62 of 1145
- Download datasheet (26Mb)
11.4.4.2
62
62
ONFI 2.2 Parameters
SAM9X25
SAM9X25
NAND Flash Boot: PMECC Error Detection and Correction
In case no valid header has been found, the Boot Program will check if the NAND Flash is ONFI
compliant, sending a Read Id command (0x90) with 0x20 as parameter for the address. If the
NAND Flash is ONFI compliant, the Boot Program retrieves the following parameters with the
help of the Get Parameter Page command:
By default, ONFI NAND Flash detection will turn ON the usePmecc parameter, and ECC correc-
tion algorithm is automatically activated.
Once the Boot Program retrieves the parameter, using one of the two methods described above,
it will read the first page again, with or without ECC, depending on the usePmecc parameter.
Then it looks for a valid code programmed just after the header offset 0xD0. If the code is valid,
the program is copied at the beginning of the internal SRAM.
Note:
NAND Flash boot procedure uses PMECC to detect and correct errors during NAND Flash read
operations in two cases:
The ROM code embeds the software used in the process of ECC detection/correction: the
Galois Field tables, and the function PMECC_CorrectionAlgo(). The user does not need to
embed it in other software.
This function can be called by user software when PMECC status returns errors after a read
page command.
Its address can be retrieved by reading the third vector of the ROM Code interrupt vector table,
at address 0x100008.
The API of this function is:
pPMECC: pointer to the PMECC base address,
pPMERRLOC: pointer to the PMERRLOC base address,
PMECC_desc: pointer to the PMECC descriptor,
PMECC_status: the status returned by the read of PMECCISR register;
• Number of bytes per page (byte 80)
• Number of bytes in spare zone (byte 84)
• Number of ECC bit correction required (byte 112)
• ECC sector size: by default set to 512 bytes, or 1024 bytes if the ECC bit capability above is
• when the usePmecc flag is set in the specific NAND header. If the flag is not set, no ECC
• when the NAND Flash has been detected using ONFI parameters.
0xFF
correction is performed during NAND Flash page read.
unsigned int PMECC_CorrectionAlgo(AT91PS_PMECC pPMECC,
Booting on 16-bit NAND Flash is not possible, only 8-bit NAND Flash memories are supported.
AT91PS_PMERRLOC pPMERRLOC,
PMECC_paramDesc_struct *PMECC_desc,
unsigned int PMECC_status,
unsigned int pageBuffer)
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
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