SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 453
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 453 of 1145
- Download datasheet (26Mb)
30.7.2
Name:
Address:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• COUNT: DDRSDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh
sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock fre-
quency (MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is pro-
grammed: (((64 x 10
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
31
23
15
–
–
–
7
DDRSDRC Refresh Timer Register
-3
)/8192) x100 x10
30
22
14
DDRSDRC_RTR
0xFFFFE804
Read-write
See
–
–
–
6
Table 30-16
29
21
13
–
–
–
5
6
= 781 or 0x030D.
28
20
12
–
–
–
4
COUNT
“DDRSDRC Write Protect Mode Register” on page
27
19
11
–
–
3
26
18
10
–
–
2
COUNT
25
17
–
–
9
1
SAM9X25
SAM9X25
466.
24
16
–
–
8
0
453
453
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