SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 739
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
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37.7.1
Name:
Address:
Access:
• DIVA, DIVB: CLKA, CLKB Divide Factor
• PREA, PREB
Values which are not listed in the table must be considered as “reserved”.
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
Value
0
1
2-255
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
31
23
15
–
–
7
PWM Mode Register
Name
CLK_OFF
CLK_DIV1
–
Name
MCK
MCKDIV2
MCKDIV4
MCKDIV8
MCKDIV16
MCKDIV32
MCKDIV64
MCKDIV128
MCKDIV256
MCKDIV512
MCKDIV1024
30
22
14
0xF8034000
–
–
6
PWM_MR
Read-write
29
21
13
–
–
5
Description
Master Clock
Master Clock divided by 2
Master Clock divided by 4
Master Clock divided by 8
Master Clock divided by 16
Master Clock divided by 32
Master Clock divided by 64
Master Clock divided by 128
Master Clock divided by 256
Master Clock divided by 512
Master Clock divided by 1024
Description
CLKA, CLKB clock is turned off
CLKA, CLKB clock is clock selected by PREA, PREB
CLKA, CLKB clock is clock selected by PREA, PREB
divided by DIVA, DIVB factor.
28
20
12
–
–
4
DIVB
DIVA
27
19
11
3
26
18
10
2
PREB
PREA
25
17
9
1
SAM9X25
SAM9X25
24
16
8
0
739
739
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