SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 520
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 520 of 1145
- Download datasheet (26Mb)
• SRC_DSCR: Source Address Descriptor
0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source.
• DST_DSCR: Destination Address Descriptor
0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination.
• FC: Flow Control
This field defines which device controls the size of the buffer transfer, also referred as to the Flow Controller.
• SRC_INCR
• DST_INCR
• IEN
If this bit is cleared, when the buffer transfer is completed, the BTC[x] flag is set in the EBCISR status register. This bit is
active low.
• AUTO: Automatic Multiple Buffer Transfer
0 (DISABLE): Automatic multiple buffer transfer is disabled.
1 (ENABLE): Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several
buffers are transferred.
520
520
SAM9X25
SAM9X25
Value
Value
Value
000
001
010
011
00
01
10
00
01
10
MEM2MEM_DMA_FC
MEM2PER_DMA_FC
PER2MEM_DMA_FC
PER2PER_DMA_FC
DECREMENTING
INCREMENTING
DECREMENTING
INCREMENTING
Name
FIXED
Name
FIXED
Name
Peripheral-to-Peripheral Transfer DMAC is flow controller
Memory-to-Peripheral Transfer DMAC is flow controller
Peripheral-to-Memory Transfer DMAC is flow controller
Memory-to-Memory Transfer DMAC is flow controller
The destination address remains unchanged
The source address remains unchanged
The destination address is decremented
The destination address is incremented
The source address is decremented
The source address is incremented
Description
Description
Description
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
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