SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 212

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

Figure 12-3. General Reset State
12.4.4.2
12.4.4.3
212
backup_nreset
periph_nreset
proc_nreset
(nrst_out)
RSTTYP
SLCK
NRST
MCK
SAM3N
Backup Reset
User Reset
A Backup reset occurs when the chip returns from Backup mode. The core_backup_reset signal
is asserted by the Supply Controller when a Backup reset occurs.
The field RSTTYP in RSTC_SR is updated to report a Backup Reset.
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in
RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behav-
ior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset
and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle
processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
T h e
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the internal reset lines remain asserted until NRST actually rises.
N R S T
XXX
EXTERNAL RESET LENGTH
M a n a g e r
= 2 cycles
Processor Startup
g u a r a n t e e s
= 2 cycles
t h a t
t h e
0x0 = General Reset
N R S T
l i n e
i s
11011A–ATARM–04-Oct-10
Freq.
Any
a s s e r t e d
XXX
f o r