SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 721

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

35.8.3.1
11011A–ATARM–04-Oct-10
Master Write Mode
Master Read Mode
Slave Read Mode
Slave Write Mode
Maximum SPI Frequency
Figure 35-15. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
NPCS0
SPCK
MISO
MOSI
The following formulas give maximum SPI frequency in Master read and write modes and in
Slave read and write modes.
The SPI is only sending data to a slave device such as an LCD, for example. The limit is
given by SPI
speed (see
pad.
T
DataFlash (AT45DB642D), T
In the formula above, F
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by
setup and hold timings SPI
the pad limit, the limit in slave read mode is given by SPCK pad.
For 3.3V I/O domain and SPI6, F
before sampling data.
f
SPCK
f
valid
SPCK
is the slave time response to output data after deleting an SPCK edge. For Atmel SPI
Max
Max
=
Section 35.8.2 “I/O
=
2
---------------------------------------------------------------------
2x S ( PI
SPI
(or SPI
--------------------------------------------------------
SPI
14
0
(
orSPI
5
6
) timing. Since it gives a maximum frequency above the maximum pad
(
orSPI
SPCK
1
3
1
SPI
)
Max = 38.0 MHz @ VDDIO = 3.3V.
7
/SPI
+
valid
9
9
)
T
Characteristics”), the max SPI frequency is the one from the
+
valid
(or T
8
SPCK
T
(or SPI
setup
SPI
Max = 32 MHz. T
v
10
) is 12 ns Max.
)
10
/SPI
11
SPI
). Since this gives a frequency well above
11
setup
is the setup time from the master
SAM3N
SPI
15
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