SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 344

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

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Free Running Processor Clock
Programmable Clock Output Controller
SAM3N
The Free running processor clock (FCLK) used for sampling interrupts and clocking debug
blocks ensures that interrupts can be sampled, and sleep events can be traced, while the pro-
cessor is sleeping. It is connected to Master Clock (MCK).
The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be indepen-
dently programmed via the PMC_PCKx registers.
PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock
(MAINCK), the PLL Clock (PLLCK) and the Master Clock (MCK) by writing the CSS field in
PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing
the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks
are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actu-
ally what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
11011A–ATARM–04-Oct-10