TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 106

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz)
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Note 2: When the timer is stopped during PDO output, the
Note 3: j = 3, 4
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the
LD
LD
LD
Setting port
(TTREG4), 3DH
(TC4CR), 00010001B
(TC4CR), 00011001B
PDOj
pin to the high level when the TimerCounter is stopped
PDOj
pin to the high level.
Page 95
: 1/1024
: Sets the operating clock to fc/2
: Starts TC4.
PDOj
pin holds the output status when the timer is
÷
2
7
/fc
÷
2 = 3DH
7
, and 8-bit PDO mode.
TMP86CS44UG