TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 41

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

2.3 Reset Circuit
Instruction
execution
RESET output
Internal reset
signal
2.3.2 Address trap reset
2.3.3 Watchdog timer reset
2.3.4 System clock reset
Note 1: Address “a” is in the SFR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Note 3: Varies on account of external condition: voltage or capacitance
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”) or the SFR area, address trap reset will be gen-
erated. The reset time is maximum 24/fc[s] (1.5μs at 16.0 MHz). Then, the
maximum 24/fc[s].
CPU. (The oscillation is continued without stopping.)
mum 24/fc[s] (1.5μs at 16.0MHz).
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alter-
Refer to Section “Watchdog Timer”.
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
The reset time is maximum 24/fc (1.5 μs at 16.0 MHz). Then, the
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
native.
JP a
Address trap is occurred
Maximum 24/fc [s]
Figure 2-16 Address Trap Reset
("L" output)
Note 3
Page 30
4/fc to 12/fc [s]
RESET
RESET
Reset release
pin outputs "L" level during maxi-
16/fc [s]
pin outputs "L" level during
Instruction at address r
TMP86CS44UG