TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 58

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

5. I/O Ports
input data should be externally held until the input data is read from outside or reading should be performed several
times before processing. Figure 5-1 shows input/output timing examples.
This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the
program.
port.
The TMP86CS44UG has 5 parallel input/output ports (35 pins) as follows.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
Note: The positions of the read and write cycles may vary, depending on the instruction.
Port P0
Port P1
Port P2
Port P3
Port P4
Data input
Output strobe
Data output
execution cycle
execution cycle
nput strobe
nstruction
nstruction
Primary Function
8-bit I/O port
8-bit I/O port
3-bit I/O port
8-bit I/O port
8-bit I/O port
Figure 5-1 Input/Output Timing (Example)
S0
S0
Fetch cycle
Fetch cycle
External interrupt input, serial and timer/counter input/output
External interrupt input, timer/counter input/output, and divider output
External interrupt input, and STOP mode release signal input
Analog input, and STOP mode release signal input
S1
S1
S2
S2
S3
S3
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Ex: LD A, (x)
Ex: LD (x), A
S0
S0
(b) Output timing
(a) nput timing
Fetch cycle
Fetch cycle
Old
S1
S1
Secondary Functions
S2
S2
S3
S3
S0
S0
Read cycle
Write cycle
S1
S1
S2
S2
New
S3
S3
TMP86CS44UG