TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 130

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

11.3.3.3 Transmit/receive mode
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK
SI pin
SIOSR<RXF>
SIOSR<RXERR>
INTSIO
interrupt
request
SIORDB
pin
(1)
The transmit/receive mode are selected by writing “10” to SIOCR1<SIOM>.
by using SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>.
to “0”.
pin.
SIOCR1<SIODIR>, synchronizing with the
starts with the direction of the bit specified by SIOCR1<SIODIR>, synchronizing with the
rising edge.
falling edge.
transferred to shift register. When 8-bit data has been received, the received data is transferred to
SIORDB from shift register, then the INTSIO interrupt request occurs, synchronizing with setting
SIOSR<RXF> to “1”.
Note: If receive error is not corrected, an interrupt request does not generate after the error occurs.
Starting the transmit/receive operation
Transmit/receive mode is selected by writing “10B” to SIOCR1<SIOM>. Serial clock is selected
When a transmit data is written to the transmit buffer register (SIOTDB), SIOSR<TXF> is cleared
After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to the falling edge of
The data is transferred sequentially starting from SO pin with the direction of the bit specified by
SIOSR<SEF> is kept in high level between the first clock falling edge of
SIOSR<TXF> is set to “1” at the rising edge of
Note 1: In internal clock operation, when the SIOCR1<SIOS> is set to "1", SIOTDB is transferred to shift
Note 2: In external clock operation, when the falling edge is input from
Figure 11-12 Example of Receive Error Processing
register after maximum 1-cycle of serial clock frequency, then a serial clock is output from
pin.
set to "1", SIOTDB is transferred to shift register immediately. When the rising edge is input from
SCK
A7 A6
pin, receive operation also starts.
Start shift
operation
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
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A
Start shift
operation
Writing transmit
data A
SCK
pin's falling edge. And receiving operation also
SCK
pin after the data written to the SIOTDB is
B
Start shift
operation
Writing transmit
data B
SCK
pin after SIOCR1<SIOS> is
Write a "0" after reading the
received data when a receive
error occurs.
SCK
pin and eighth clock
TMP86CS44UG
SCK
SCK
pin's
SCK