TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 128

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK
SI pin
SIOSR<RXF>
INTSIO
interrupt
request
SIORDB
pin
Figure 11-10 Example of Internal Clock and MSB Receive Mode
(3)
tion is finished. Then INTSIO interrupt request is generated after SIOSR<RXERR> is set to “1”.
If received data is not read out from SIORDB receive error occurs immediately after shift opera-
Stopping the receive operation
There are two ways for stopping the receive operation.
A7
• The way of clearing SIOCR1<SIOS>.
• The way of setting SIOCR1<SIOINH>.
A6 A5 A4 A3 A2 A1
When SIOCR1<SIOS> is cleared to “0”, receive operation is stopped after all of the data is
finished to receive. When receive operation is finished, SIOSR<SIOF> is cleared to “0”.
In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is
set to “1” by starting the next shift operation.
Receive operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this case,
SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initialized.
Start shift
operation
Automatic wait
A0
A
Writing transmit
data A
Page 117
B7 B6 B5 B4 B3 B2 B1
Start shift
operation
Writing transmit
data B
B0
B
C7
Start shift
operation
C6 C5 C4 C3 C2 C1 C0
Clearing SIOS
TMP86CS44UG
Writing transmit
data C
C