TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 133

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

11.3 Function
SI pin
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK
SO pin
INTSIO
interrupt
request
SIOSR<TXF>
SIOTDB
SIOSR<RXF>
SIORDB
pin output
Figure 11-14 Example of External Clock and MSB Transmit/Receive Mode
(4)
errors occur transmits or receives.
Writing transmit
data A
Transmit/receive error processing
Transmit/receive errors occur on the following situation. Corrective action is different, which
(a) Transmit errors
A
Transmit errors occur on the following situation.
• Shift operation starts before writing next transmit data to SIOTDB in external clock op-
A7 A6
D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0
eration.
If transmit errors occur during transmit operation, SIOSR<TXERR> is set to “1” imme-
diately after starting shift operation. And INTSIO interrupt request is generated after all
of the 8-bit data has been received.
If shift operation starts before writing data to SIOTDB after SIOCR1<SIOS> is set to
“1”, SIOSR<TXERR> is set immediately after starting shift operation. And INTSIO in-
terrupt request is generated after all of the 8-bit data has been received.
SO pin is kept in high level when SIOSR<TXERR> is set to “1”. When transmit error
occurs, transmit operation must be forcibly stop by writing SIOCR1<SIOINH> to “1”
after the received data is read from SIORDB. In this case, SIOCR1<SIOS>, SIOSR reg-
ister, SIORDB register and SIOTDB register are initialized.
Writing transmit data
Start shift
operation
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Reading received
data D
Writing transmit
data B
Reading received data
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D
B
Start shift
operation
Writing transmit
data C
Reading received
data E
E
C
Start shift
operation
Clearing SIOS
Reading received
data F
F
TMP86CS44UG