TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 144
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMP86xy44UG
Manufacturer Part Number
TMP86xy44UG
Description
Manufacturer
Toshiba
Datasheet
1.TMP86XY44UG.pdf
(173 pages)
Specifications of TMP86xy44UG
Package
QFP44
Rom Types (m=mask,p=otp,f=flash)
M/P
Rom Size
60
Ram Size
1K
Driver Led
19
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
1
I2c/sio Channels
-
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
8
Da Converter Channels
1
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
35
Power Supply (v)
4.5 to 5.5
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TDBUF
TXD pin
UARTSR<TBEP>
INTTXD interrupt
Shift register
12.9.6 Transmit End Flag
TXD pin
UARTSR<TBEP>
UARTSR<TEND>
INTTXD interrupt
Shift register
Figure 12-10 Generation of Transmit End Flag and Transmit Data Buffer Empty
UARTSR<TEND> is set to “1”. The UARTSR<TEND> is cleared to “0” when the data transmit is started after
writing the TDBUF.
When data are transmitted and no data is in TDBUF (UARTSR<TBEP> = “1”), transmit end flag
***** 1
xxxx
Figure 12-9 Generation of Transmit Data Buffer Empty
***
1xx
1xxxx0
Start
****
Data write
* 1xxxx
1x
Bit 0
yyyy
***** 1
Stop
Page 133
Data write for TDBUF
Final bit
**** 1x
***** 1
Stop
After reading UARTSR writing TDBUF
clears TBEP.
1yyyy0
1yyyy0
Start
zzzz
Data write
TMP86CS44UG
* 1yyyy
Bit 0
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