MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet
MSC8102D
Related parts for MSC8102D
MSC8102D Summary of contents
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Technical Data Advance Information MSC8102/D Rev. 2, 4/2003 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core MQBus Boot ROM The raw processing power of this highly integrated system-on- a-chip device enables PLL/Clock developers to create next generation JTAG Port ...
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Table of Contents Features .............................................................................................................................................................. iv Product Documentation.................................................................................................................................... viii Chapter 1 Signal/ Connection Description 1.1 Power Signals................................................................................................................................................... 1-3 1.2 Clock Signals ................................................................................................................................................... 1-3 1.3 Reset and Configuration Signals...................................................................................................................... 1-4 1.4 Direct Slave Interface, System Bus, and Interrupt Signals .............................................................................. 1-4 ...
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Address Data ALU Program Register Register Sequencer File File Address Data SC140 ALU ALU Core JTAG EOnCE™ Power Management SC140 Core EOnCE™ 128 P Instruction Cache 128 QBus PIC IRQs LIC IRQs MQBus SQBus Local Bus ...
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Features • Four high-performance StarCore SC140 Digital Signal Processor (DSP) extended cores delivering up to 4400 MMACS using 16 ALUs running 275 MHz, delivering a performance equivalent to a single SC140 core running at 1.1 GHz • ...
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Variable block sizes ( GB). ° Selectable memory controller machine. ° Two types of data errors check/correction (on 60x-compatible system bus only): Normal ° odd/even parity and Read-modify-write (RMW) odd/even ...
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Hardware A-law/ -law conversion — Mbps per TDM (50 MHz bit clock if one data line is used, 25 MHz if two data lines are used, 12.5 MHz if four data lines are used). — Up ...
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Single-wire and loop operations. • Timers — Two modules of 16 timers each. — Each timer has the following features: Cyclic or one-shot. ° Input clock polarity control. ° Interrupt request when counting reaches a programmed threshold. ° Pulse ...
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Boot options: ° ° ° ° • Power: — Requires separate power supplies for on-chip logic (1.6 V) and I/O (3.3 V) — Provides low-power standby modes — Includes optimized power ...
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Chapter 1 Signal/ Connection Description The MSC8102 external signals are organized into functional groups, as shown in Table 1-1 and Figure 1-1.. Table 1-1 lists the functional groups, the number of signal connections in each group, and references the table ...
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HD[32–63]/D[32–63] HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3] HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/ PWE[4–7]/PSDDQM[4–7]/PBS[4–7] HRDS/HRW/HRDE GPIO0/CHIP_ID0/IRQ4 GPIO1/TIMER0/CHIP_ID1/IRQ5 GPIO2/TIMER1/CHIP_ID2/IRQ6 GPIO3/TDM3TSYN/IRQ1 GPIO4/TDM3TCLK/IRQ2 GPIO5/TDM3TDAT/IRQ3 GPIO6/TDM3RSYN/IRQ4 GPIO7/TDM3RCLK/IRQ5 GPIO8/TDM3RDAT/IRQ6 GPIO9/TDM2TSYN/IRQ7 GPIO10/TDM2TCLK/IRQ8 GPIO11/TDM2TDAT/IRQ9 GPIO12/TDM2RSYN/IRQ10 GPIO13/TDM2RCLK/IRQ11 GPIO14/TDM2RDAT/IRQ12 GPIO15/TDM1TSYN/DREQ1 GPIO16/TDM1TCLK/DONE1/DRACK1 GPIO17/TDM1TDAT/DACK1 GPIO18/TDM1RSYN/DREQ2 GPIO19/TDM1RCLK/DACK2 GPIO20/TDM1RDAT GPIO21/TDM0TSYN GPIO22/TDM0TCLK/DONE2/DRACK2 GPIO23/TDM0TDAT/IRQ13 GPIO24/TDM0RSYN/IRQ14 GPIO25/TDM0RCLK/IRQ15 GPIO26/TDM0RDAT GPIO27/URXD/DREQ1 GPIO28/UTXD/DREQ2 GPIO29/CHIP_ID3 GPIO30/TIMER2/TMCLK Power signals include: V ...
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Power Signals Signal Name DDH V CCSYN GND GND SYN 1.2 Clock Signals Signal Name CLKIN CLKOUT DLLIN Table 1-2. Power and Ground Signal Inputs Internal Logic Power V dedicated for use with the device core. ...
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Reset and Configuration Signals 1.3 Reset and Configuration Signals Signal Name PORESET RSTCONF HRESET SRESET Note: 1.4 Direct Slave Interface, System Bus, and Interrupt Signals The direct slave interface (DSI) is combined with the system bus because they share some ...
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Table 1-5. DSI, System Bus, and Interrupt Signals (Continued) Signal Name Type HD2 Input/ Host Data Bus 2 Output Bit 2 of the DSI data bus. DSI64 Input DSI 64 Defines the width of the DSI and SYSTEM Data buses. ...
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Direct Slave Interface, System Bus, and Interrupt Signals Signal Name HWBS[4–7] HDBS[4–7] HWBE[4–7] HDBE[4–7] PWE[4–7] PSDDQM[4–7] PBS[4–7] HRDS HRW HRDE HBRST HDST0 HDST1 HCS HBCS HTA HCLKIN 1-6 Table 1-5. DSI, System Bus, and Interrupt Signals (Continued) Type Input Host ...
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Table 1-5. DSI, System Bus, and Interrupt Signals (Continued) Signal Name Type A[0–31] Input/ Address Bus Output When the MSC8102 is in external master bus mode, these pins function as the system address bus. The MSC8102 drives the address of ...
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Direct Slave Interface, System Bus, and Interrupt Signals Signal Name IRQ5 BADDR29 BADDR28 BADDR27 BR BG DBG ABB IRQ4 DBB IRQ5 TS AACK 1-8 Table 1-5. DSI, System Bus, and Interrupt Signals (Continued) Type 1 Input Interrupt Request 5 One ...
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Table 1-5. DSI, System Bus, and Interrupt Signals (Continued) Signal Name Type ARTRY Input/ Address Retry Output Assertion of this signal indicates that the bus master should retry the bus transaction. An external master asserts this signal to enforce data ...
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Direct Slave Interface, System Bus, and Interrupt Signals Signal Name IRQ3 DP3 DREQ2 EXT_BR3 IRQ4 DP4 DACK3 EXT_DBG3 IRQ5 DP5 DACK4 EXT_BG3 IRQ6 DP6 DREQ3 1-10 Table 1-5. DSI, System Bus, and Interrupt Signals (Continued) Type Input Interrupt Request 3 ...
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Table 1-5. DSI, System Bus, and Interrupt Signals (Continued) Signal Name Type IRQ7 Input Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP7 Input/ System ...
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Memory Controller Signals 1.5 Memory Controller Signals Refer to the Memory Controller chapter in the MSC8102 Reference Manual for detailed information about configuring these signals. Signal Name BCTL0 BCTL1 CS5 BM[0–2] TC[0–2] BNKSEL[0–2] ALE PWE[0–3] PSDDQM[0–3] PBS[0–3] PSDA10 PGPL0 PSDWE ...
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Table 1-6. Memory Controller Signals (Continued) Signal Name Type POE Output System Bus Output Enable From the bus GPCM. Controls the output buffer of memory devices during read operations. PSDRAS Output System Bus SDRAM RAS From the bus SDRAM controller. ...
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GPIO, TDM, UART, and Timer Signals 1.6 GPIO, TDM, UART, and Timer Signals The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines. Individual ...
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Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued) Signal Name Type GPIO4 Input/ General-Purpose Input Output 4 Output One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. ...
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GPIO, TDM, UART, and Timer Signals Signal Name GPIO8 TDM3RDAT IRQ6 GPIO9 TDM2TSYN IRQ7 GPIO10 TDM2TCLK IRQ8 GPIO11 TDM2TDAT IRQ9 1-16 Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued) Type Input/ General-Purpose Input Output 8 Output One of 32 ...
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Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued) Signal Name Type GPIO12 Input/ General-Purpose Input Output 12 Output One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. ...
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GPIO, TDM, UART, and Timer Signals Signal Name GPIO16 TDM1TCLK DONE1 DRACK1 GPIO17 TDM1TDAT DACK1 GPIO18 TDM1RSYN DREQ2 GPIO19 TDM1RCLK DACK2 1-18 Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued) Type Input/ General-Purpose Input Output 16 Output One of ...
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Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued) Signal Name Type GPIO20 Input/ General-Purpose Input Output 20 Output One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. ...
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GPIO, TDM, UART, and Timer Signals Signal Name GPIO24 TDM0RSYN IRQ14 GPIO25 TDM0RCLK IRQ15 GPIO26 TDM0RDAT GPIO27 URXD GPIO28 UTXD GPIO29 CHIP_ID3 1-20 Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued) Type Input/ General-Purpose Input Output 24 Output One ...
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Table 1-7. GPIO, TDM, UART, and Timer Signals (Continued) Signal Name Type GPIO30 Input/ General-Purpose Input Output 30 Output One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For ...
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EOnCE Event and JTAG Test Access Port Signals 1.7 EOnCE Event and JTAG Test Access Port Signals The MSC8102 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the JTAG TAP controller. Each ...
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Chapter 2 Specifications 2.1 Introduction This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8102 User’s Manual and MSC8102 Reference Manual. Note: The MSC8102 electrical specifications are preliminary and ...
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Maximum Ratings 2.2 Maximum Ratings In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of ...
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Recommended Operating Conditions Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Core supply voltage PLL supply voltage I/O supply voltage Input voltage Operating temperature range 2.4 Thermal Characteristics Table 2-3 describes ...
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DC Electrical Characteristics 2.5 DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8102. The measurements in Table 2-4 assume the following system conditions: • 0–70 °C A • 1.55–1 • ...
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AC Timings 2.6.1 Load Assumptions The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based load, except where noted otherwise, and a 50 line. ...
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AC Timings 1 CLKIN • Frequency • Cycle time 1 DLLIN • Frequency • Cycle time Reference Clock (REFCLK) • Frequency • Cycle time Output Clock (CLKOUT) • Frequency • Cycle time SC140 core clock • Frequency • Cycle time ...
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Name Direction External Soft Input/ Initiates the soft reset flow. The MSC8102 detects an external assertion of SRESET reset Output only if it occurs while the MSC8102 is not asserting reset. SRESET is an open-drain (SRESET) pin. Upon soft reset, ...
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AC Timings 2.6.3.1 Power-On Reset (PORESET) Pin Asserting 16 CLKIN 2.6.3.2 Reset Configuration The MSC8102 has two mechanisms for writing the reset configuration: • Through the direct slave interface (DSI), or • Through the system bus When reset configuration written ...
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Table 2-10. Timing for a Reset Configuration Write through the DSI or System Bus No. Characteristics 5 • Delay from SPLL and DLL lock to HRESET de-assertion • DLL enabled REFCLK = 18 Mhz REFCLK = 75 Mhz • DLL ...
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AC Timings 2.6.4 System Bus Access Timing 2.6.4.1 Core Data Transfers Generally, all MSC8102 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is either the Memory controller signals, however, trigger ...
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Table 2-13. AC Timing for SIU Outputs for Non-Pipelined Mode No. 31 PSDVAL/TEA/TA delay from REFCLK rising edge 32a Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL delay from REFCLK rising edge 32b BADDR delay from REFCLK rising edge 33a Data bus delay ...
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AC Timings Table 2-16. AC Timing for SIU Outputs for Pipelined Mode No. 31 PSDVAL/TEA/TA delay from REFCLK rising edge 32a Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL delay from REFCLK rising edge 32b BADDR delay from REFCLK rising edge 33a Data ...
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DMA Data Transfers Table 2-17 describes the DMA signal timing. No. Characteristic 37 DREQ setup time before falling edge of REFCLK 38 DREQ hold time after falling edge of REFCLK 39 DONE setup time before falling edge of REFCLK ...
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AC Timings 2.6.5 DSI Timing The timings in the following sections are based capacitive load. See Section 2.6.1, Load Assumptions, on page 5 for more details. 2.6.5.1 DSI Asynchronous Mode No. 1 100 Attributes setup time ...
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Figure 2-5 shows DSI Asynchronous Read signals timing. HCS HA[11–29] HCID[0–4] HDST 1 HRW 2 HWBSn 1 HDBSn 2 HRDS HD[0–63] 3 HTA 4 HTA Notes: 1. Used for Single Strobe mode access. 2. Used for Dual Strobe mode access. ...
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AC Timings Figure 2-6 shows DSI Asynchronous Write signals timing. 2-16 HCS HA[11–29] HCID[0–4] HDST 1 HRW 100 2 HRDS 1 HDBSn 2 HWBSn HD[0–63] 106 3 HTA 108 4 HTA Notes: 1. Used for Single Strobe mode access. 2. ...
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Figure 2-7 shows DSI Asynchronous Broadcast Write signals timing. HCS HA[11–29] HCID[0–4] HDST 1 HRW 100 2 HRDS 1 HDBSn 2 HWBSn HD[0–63] 3 HTA 4 HTA Notes: 1. Used for Single Strobe mode access. 2. Used for Dual Strobe ...
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AC Timings 2.6.5.2 DSI Synchronous Mode Number 120 121 122 123 124 125 126 Notes: Number 127 128 129 130 131 132 133 134 HD[0–63], HA[11–29] HCID[0–4] input signals All other input signals HD[0–63] output signals HTA output signal 2-18 ...
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TDM Timing . Number 300 301 302 303 304 305 306 307 308 309 310 Notes: TDMxRDAT Table 2-21. TDM Timing Characteristic TDMxRCLK/TDMxTCLK TDMxRCLK/TDMxTCLK High Pulse Width TDMxRCLK/TDMxTCLK Low Pulse Width TDM receive all input Setup time TDM receive ...
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AC Timings 2.6.7 UART Timing No. 400 URXD and UTXD inputs high/low duration 401 URXD and UTXD inputs rise/fall time 402 UTXD output rise/fall time UTXD, URXD inputs UTXD output 2-20 Table 2-22. UART Timing Characteristics 401 400 Figure 2-11. ...
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Timer Timing TIMERx (Input) TIMERx (Output) No. 500 501 502 503 500 501 503 Figure 2-13. Timer Timing Table 2-23. Timer Timing Characteristics TIMERx frequency TIMERx Input high period TIMERx Output low period TIMERx Propagations delay from its clock ...
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AC Timings 2.6.9 GPIO Timing No. 601 602 603 604 605 REFCLK (Output) GPIO (Output) GPIO (Input) 2-22 Table 2-24. GPIO Timing Characteristics REFCLK edge to GPIO out valid (GPIO out delay time) REFCLK edge to GPIO out not valid ...
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EE Signals Number 65 66 Notes: Figure 2-15 shows the signal behavior of the EE pins. Table 2-25. EE Pin Timing Characteristics EE pins as inputs EE pins as outputs 1. The core clock is the SC140 core clock. ...
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AC Timings 2.6.11 JTAG Signals No. 700 TCK frequency of operation (1/(T 701 TCK cycle time in Crystal mode 702 TCK clock pulse width measured at V 703 TCK rise and fall times 704 Boundary scan input data set-up time ...
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TCK V (Input) IL Data Inputs Data Outputs Data Outputs Figure 2-17. Boundary Scan (JTAG) Timing Diagram TCK V (Input) IL TDI TMS (Input) 710 TDO (Output) 711 TDO (Output) Figure 2-18. Test Access Port Timing Diagram TCK (Input) 713 ...
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AC Timings 2-26 ...
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Chapter 3 Packaging 3.1 Pinout and Package Information This sections provides information about the MSC8102 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1, Signal/Connection Descriptions are allocated. The MSC8102 is available ...
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FC-CBGA (HCTE) Package Description NMI_ B V GND GND GND DD OUT GND TDO GPIO28 HCID1 DD RESET D TDI EE0 EE1 GND V HCID2 DDH TCK TRST TMS HRESET GPIO27 HCID0 ...
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B GND V V GPIO0 V GND GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 D GPIO8 GND V GPIO4 V GPIO29 GPIO31 DDH DDH GND GPIO12 GPIO10 GPIO13 GPIO9 GND ...
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FC-CBGA (HCTE) Package Description 3-4 Table 3-1. MSC8102 Signal Listing By Name Signal Name A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BM0 BM1 BM2 BR CHIP_ID0 CHIP_ID1 CHIP_ID2 CHIP_ID3 CLKIN CLKOUT CNFGS CS0 CS1 CS2 CS3 CS4 CS5 CS5 ...
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FC-CBGA (HCTE) Package Description Table 3-1. MSC8102 Signal Listing By Name (Continued) 3-6 Location Signal Name Designator D10 V10 D11 U10 D12 V11 D13 V12 D14 ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DACK1 DACK1 DACK2 DACK2 ...
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FC-CBGA (HCTE) Package Description Table 3-1. MSC8102 Signal Listing By Name (Continued) 3-8 Location Signal Name Designator DONE1 F19 DONE2 G22 DP0 P19 DP1 T18 DP2 R19 DP3 R17 DP4 T17 DP5 T16 DP6 R16 DP7 R15 DRACK1 F19 DRACK2 ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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FC-CBGA (HCTE) Package Description Table 3-1. MSC8102 Signal Listing By Name (Continued) 3-10 Location Signal Name Designator GND L10 GND L14 GND L16 GND L17 GND M5 GND M6 GND M7 GND M10 GND M14 GND M19 GND N10 GND ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 ...
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FC-CBGA (HCTE) Package Description Table 3-1. MSC8102 Signal Listing By Name (Continued) 3-12 Location Signal Name Designator HA14 L3 HA15 K2 HA16 K4 HA17 G6 HA18 J2 HA19 H5 HA20 H2 HA21 K3 HA22 F6 HA23 G5 HA24 G2 HA25 ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 ...
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FC-CBGA (HCTE) Package Description Table 3-1. MSC8102 Signal Listing By Name (Continued) 3-14 Location Signal Name Designator HD46 AA15 HD47 AB15 HD48 AB14 HD49 AB13 HD50 AB12 HD51 Y11 HD52 AA11 HD53 AB11 HD54 AA10 HD55 AB10 HD56 AB9 HD57 ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name HWBS2 HWBS3 HWBS4 HWBS5 HWBS6 HWBS7 INT_OUT IRQ1 IRQ1 IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ4 IRQ4 IRQ5 IRQ5 IRQ5 IRQ5 IRQ6 IRQ6 IRQ7 IRQ7 IRQ7 IRQ8 IRQ9 ...
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FC-CBGA (HCTE) Package Description Table 3-1. MSC8102 Signal Listing By Name (Continued) 3-16 Location Signal Name Designator IRQ15 J21 MODCK1 V2 MODCK2 W4 MWBE4 R7 MWBE5 T7 MWBE6 R6 MWBE7 T6 NMI F4 NMI_OUT B6 PBPL3 H7 PBS0 G7 PBS1 ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE PWE0 PWE1 PWE2 PWE3 PWE4 PWE5 PWE6 PWE7 PUPMWAIT RSTCONF SRESET SWTE TA TBST TC0 TC1 TC2 TCK TDI TDM0RCLK TDM0RDAT TDM0RSYN TDM0TCLK TDM0TDAT ...
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FC-CBGA (HCTE) Package Description Table 3-1. MSC8102 Signal Listing By Name (Continued) 3-18 Location Signal Name Designator TDM1TDAT G21 TDM1TSYN G19 TDM2RCLK E20 TDM2RDAT F21 TDM2RSYN E22 TDM2TCLK E21 TDM2TDAT F20 TDM2TSYN E19 TDM3RCLK C19 TDM3RDAT D22 TDM3RSYN C22 TDM3TCLK ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name UTXD V CCSYN ...
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FC-CBGA (HCTE) Package Description Table 3-1. MSC8102 Signal Listing By Name (Continued) 3-20 Location Signal Name Designator V H15 DD V H20 J13 DD V J15 DD V K15 ...
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Table 3-1. MSC8102 Signal Listing By Name (Continued) Signal Name V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH V DDH Note: This table lists ...
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FC-CBGA (HCTE) Package Description Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) 3-22 Number Signal Name B18 V DD B19 GPIO0/CHIP_ID0 B20 V DD B21 V DD B22 GND C2 GND TDO C5 SRESET C6 ...
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Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) Number D11 D12 D13 D14 D15 D16 D17 D18 D19 GPIO4/TDM3TCLK/IRQ2 D20 D21 D22 GPIO8/TDM3RDAT/IRQ6 E10 E11 E12 E13 E14 E15 E16 E17 ...
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FC-CBGA (HCTE) Package Description Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) 3-24 Number Signal Name F4 NMI F5 HA29 F6 HA22 F7 GND F10 V DD F11 GND F12 V DD F13 ...
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Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) Number G18 G19 GPIO15/TDM1TSYN/DREQ1 G20 G21 GPIO17/TDM1TDAT/DACK1 G22 GPIO22/TDM0TCLK/DONE2/DRACK2 PGTA/PUPMWAIT/PGPL4/PPBS H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 GPIO24/TDM0RSYN/IRQ14 H19 GPIO21/TDM0TSYN H20 ...
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FC-CBGA (HCTE) Package Description Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) 3-26 Number Signal Name J11 BM2/TC2/BNKSEL2 J12 DBG J13 V DD J14 GND J15 V DD J16 TT3/CS6 J17 PSDA10/PGPL0 J18 BCTL1/CS5 J19 GPIO23/TDM0TDAT/IRQ13 J20 GND J21 ...
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Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) Number L10 L14 L15 L16 L17 L18 L19 L20 L21 L22 M10 M14 M15 M16 M17 M18 ...
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FC-CBGA (HCTE) Package Description Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) 3-28 Number Signal Name N3 HD30 N4 HD29 N5 HD24 N6 PWE2/PSDDQM2/PBS2 N7 V DDH N8 HWBS0 N9 HBCS N10 GND N14 GND N15 HRDS/HRW/HRDE N16 BG ...
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Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) Number P20 P21 P22 HWBS6/HDBS6/MWBE6/HDBE6/PWE6/ R7 HWBS4/HDBS4/MWBE4/HDBE4/PWE4 R10 R11 R12 R13 R14 R15 R16 R17 IRQ3/DP3/DREQ2/EXT_BR3 R18 R19 IRQ2/DP2/DACK2/EXT_DBG2 R20 R21 R22 T2 T3 ...
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FC-CBGA (HCTE) Package Description Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) 3-30 Number Signal Name T11 V DD T12 D16 T13 TT1 T14 D21 T15 D23 T16 IRQ5/DP5/DACK4/EXT_BG3 T17 IRQ4/DP4/DACK3/EXT_DBG3 T18 IRQ1/DP1/DACK1/EXT_BG2 T19 D30 T20 GND T21 A15 ...
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Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) Number V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W10 W11 W12 ...
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FC-CBGA (HCTE) Package Description Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) 3-32 Number Signal Name W18 HD32/D32 W19 GND W20 GND W21 A7 W22 A6 Y2 HD7 Y3 HD15 Y4 V DDH Y5 HD9 ...
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Table 3-2. MSC8102 Signal Listing by Ball Designator (Continued) Number AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 ...
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FC-CBGA (HCTE) Package Mechanical Drawing 3.3 FC-CBGA (HCTE) Package Mechanical Drawing Figure 3-3. MSC8102 Mechanical Information, 431-pin FC-CBGA (HCTE) Package 3-34 CASE 1453-02 Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M–1994. 3. Maximum solder ball ...
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FC-PBGA Package Mechanical Drawing Figure 3-4. MSC8102 Mechanical Information, 431-pin FC-PBGA Package Note: CASE 1385-01 This package is used for pre-production MSC8102 devices only. The package may include a copper lid. Addition of the copper lid increases the overall ...
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FC-PBGA Package Mechanical Drawing 3-36 ...
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Chapter 4 Design Considerations 4.1 Thermal Design Considerations The average chip-junction temperature Equation 1: T where • ambient temperature C A • = package thermal resistance JA • INT • INT ...
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Connectivity Guidelines Figure 4-2 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on ...
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In single master mode, value. In other modes, they must be pulled up. • If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, Otherwise, it should be pulled up. • The following signals: MSC8102 and are ...
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Layout Practices 4.5 Layout Practices Each V CC power supply. Similarly, each power supply pins drive distinct groups of logic on the chip. The to ground using at least four 0.1 µF by-pass capacitors located as closely as possible to ...
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Ordering Information Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order. Supply Part Voltage MSC8102 1.6 V core High Temperature Coefficient for Expansion Flip Chip 3.3 V I/O Ceramic Ball Grid Array ...