MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 4

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Features
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• Four high-performance StarCore SC140 Digital Signal Processor (DSP) extended cores delivering up
• Each extended core includes:
• Each SC140 core provides the following:
• Large internal memory spaces (1.440 MB total).
• Internal PLL for generating up to 275 MHz clock for the SC140 cores and up to 91.67 MHz for the
• Very flexible System Interface Unit (SIU) with a memory controller to support a 32/64-bit wide
• Flexible eight-bank memory controller:
to 4400 MMACS using 16 ALUs running at up to 275 MHz, delivering a performance equivalent to a
single SC140 core running at 1.1 GHz
— SC140 core processor.
— Local 224 KB memory space (M1) accessed by the SC140 core with no wait states and atomic
— 16 KB, 16-way instruction cache (ICache).
— Programmable interrupt controller (PIC).
— Local interrupt controller (LIC).
— Up to 1100 million multiply-accumulates per second (MMACS) using an internal 275 MHz clock
— 4 ALUs per SC140 core.
— 16 data registers, 40 bits each.
— 27 address registers, 32 bits each.
— Hardware support for fractional and integer data types.
— Very rich 16-bit wide orthogonal instruction set.
— Up to six instructions executed in a single clock cycle.
— Variable-length execution set (VLES) that can be optimized for code density and performance.
— IEEE 1149.1 JTAG port.
— Enhanced on-device emulation (EOnCE) module with real-time debugging capabilities.
— 224 KB of M1 memory per core (896 KB total).
— 16 KB of ICache per core (64 KB total).
— 476 KB shared memory (M2) operating at the core frequency, accessible from all four SC140
— 4 KB boot ROM accessible from all four SC140 cores via the MQBus.
60x-compatible system bus, the local bus and other modules. PLL values are determined at reset based
on configuration signal values.
60x-compatible system bus to access memory and memory-mapped devices:
— Reset controller.
— Real-time clock register.
— Periodic interrupt timer (PIT).
— Hardware bus monitors for the 60x-compatible system bus and local bus.
— Software watchdog timer function.
— Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, FLASH and other
— Byte enables for either 64-bit or 32-bit bus width mode.
— Eight external memory banks (banks 0–7). Two additional memory banks control IPBus
access.
at 1.6 V. A multiply-accumulate operation includes a multiply-add instruction with the associated
data move and pointer update.
cores via the MQBus, and accessible from the local bus.
page-mode SDRAM machine.
user-definable peripherals.
peripherals and internal memories (banks 9, 11). Each bank has the following features: