MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 41

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Notes:
Notes:
Note:
No.
No.
No.
32a Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL delay from REFCLK rising edge
32b BADDR delay from REFCLK rising edge
33a Data bus delay from REFCLK rising edge
33b DP delay from REFCLK rising edge
32a Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL delay from REFCLK rising edge
32b BADDR delay from REFCLK rising edge
33a Data bus delay from REFCLK rising edge
33b DP delay from REFCLK rising edge
32a Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL delay from REFCLK rising edge
32b BADDR delay from REFCLK rising edge
33a Data bus delay from REFCLK rising edge
33b DP delay from REFCLK rising edge
31
34
35
36
31
34
35
36
31
34
35
36
PSDVAL/TEA/TA delay from REFCLK rising edge
Memory controller signals/ALE delay from REFCLK rising edge
DBG/BR/ABB/CS delay from REFCLK rising edge
Delay from REFCLK rising edge for all other signals
PSDVAL/TEA/TA delay from REFCLK rising edge
Memory controller signals/ALE delay from REFCLK rising edge
DBG/BR/ABB/CS delay from REFCLK rising edge
Delay from REFCLK rising edge for all other signals
PSDVAL/TEA/TA delay from REFCLK rising edge
Memory controller signals/ALE delay from REFCLK rising edge
DBG/BR/ABB/CS delay from REFCLK rising edge
Delay from REFCLK rising edge for all other signals
1.
2.
1.
2.
3.
Values are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level (0.8 or 2 V)
In 60x-compatible mode with SIUBCR[EBM] = 1.
Values are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level (0.8 or 2 V)
The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8102 device, the frequency is determined by adding the input and output
longest timing values, which results in a frequency of 80 MHz.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8102.
In single master mode with SIUBCR[EBM] = 0.
Values are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level (0.8 or 2 V)
Table 2-13. AC Timing for SIU Outputs for 30 pF in Non-Pipelined Mode
Table 2-15. AC Timing for SIU Outputs for 50 pF in Non-Pipelined Mode
Table 2-14. AC Timing for SIU Outputs for 30pF in Pipelined Mode
Characteristic
Characteristic
Characteristic
Minimum Maximum
Minimum Maximum
Minimum Maximum
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7.5
7.5
7.5
6.5
6.5
6.5
6.5
6.5
9.5
8.5
9.5
9.5
8.5
10
8
6
8
7
6
6
7
6
8
8
1
2
AC Timings
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-11