MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 38

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

AC Timings
2-8
2.6.3.1 Power-On Reset (PORESET) Pin
Asserting
16
2.6.3.2 Reset Configuration
The MSC8102 has two mechanisms for writing the reset configuration:
• Through the direct slave interface (DSI), or
• Through the system bus
When reset configuration written through the system bus, the MSC8102 uses as a configuration master or
as a configuration slave. If a configuration slave is selected, but no special configuration word is written,
a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on
deassertion to define the Reset Configuration Mode and boot and operating conditions:
•
•
•
•
•
•
•
•
2.6.3.3 Reset Timing Tables
Table 2-10 and Figure 2-1 describe the reset timing for a reset configuration write through the direct
slave interface (DSI) or through the system bus.
No.
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
CLKIN
1
2
3
4
Table 2-10. Timing for a Reset Configuration Write through the DSI or System Bus
Required external PORESET duration minimum
•
•
Delay from deassertion of external PORESET to
deassertion of internal PORESET
•
•
Delay from de-assertion of internal PORESET to
SPLL lock
•
•
Delay from SPLL lock to DLL lock.
•
•
PORESET
cycles after external power to the MSC8102 reaches at least 2/3
CLKIN = 18 MHz
CLKIN = 75 MHz
CLKIN = 18 MHz
CLKIN = 75 MHz
CLKIN = 18 MHz
CLKIN = 75 MHz
REFCLK = 75 Mhz
DLL disabled
DLL enabled
REFCLK = 18 Mhz
initiates the power-on reset flow.
Characteristics
PORESET
(pre-division factor)
800 / (CLKIN/PDF)
3073 / REFCLK
Expression
1024 / CLKIN
16 / CLKIN
—
must be asserted externally for at least
V
888.8
213.3
Min
DD
.
170.72
58.89
13.65
40.97
44.4
32.0
0.0
PORESET
Max
—
Unit
ns
s
s
s
s
s
s
s