MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 21
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MSC8102D
Manufacturer Part Number
MSC8102D
Description
Quad Core 16-Bit Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.MSC8102D.pdf
(100 pages)
- Current page: 21 of 100
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Signal Name
POE
PSDRAS
PGPL2
PSDCAS
PGPL3
PGTA
PUPMWAIT
PGPL4
PPBS
PSDAMUX
PGPL5
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
Input
Table 1-6. Memory Controller Signals (Continued)
System Bus Output Enable
From the bus GPCM. Controls the output buffer of memory devices during read
operations.
System Bus SDRAM RAS
From the bus SDRAM controller. Should connect to SDRAM RAS input.
System Bus UPM General-Purpose Line 2
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
System Bus SDRAM CAS
From the bus SDRAM controller. Should connect to SDRAM CAS input.
System Bus UPM General-Purpose Line 3
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
System GPCM TA
Terminates external transactions during GPCM operation. Requires an external pull-up
resistor for proper operation.
System Bus UPM Wait
An external device holds this pin low to force the UPM to wait until the device is ready to
continue the operation.
System Bus UPM General-Purpose Line 4
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
System Bus Parity Byte Select
In systems that store data parity in a separate chip, this output is used as the byte-select
for that chip.
System Bus SDRAM Address Multiplexer
Controls the system bus SDRAM address multiplexer when the MSC8102 is in external
master mode.
System Bus UPM General-Purpose Line 5
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
Description
Memory Controller Signals
1-13
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