MSC8102D Motorola / Freescale Semiconductor, MSC8102D Datasheet - Page 14

• Manufacturer Part Number: MSC8102D
• Description: Quad Core 16-Bit Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Direct Slave Interface, System Bus, and Interrupt Signals
1-6
Signal Name
HWBS[4–7]
HDBS[4–7]
HWBE[4–7]
HDBE[4–7]
PWE[4–7]
PSDDQM[4–7]
PBS[4–7]
HRDS
HRW
HRDE
HBRST
HDST0
HDST1
HCS
HBCS
HTA
HCLKIN
Output
Output
Output
Output
Type
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Host Write Byte Strobes (In Asynchronous dual mode)
One bit per byte is used as a strobe for host write accesses.
Host Data Byte Strobe (in Asynchronous single mode)
One bit per byte is used as a strobe for host read or write accesses
Host Write Byte Enable (In Synchronous dual mode)
One bit per byte is used to indicate a valid data byte for host write accesses.
Host Data Byte Enable (in Synchronous single mode)
One bit per byte is used as a strobe enable for host read or write accesses
System Bus Write Enable
Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte
lanes for write operations.
System Bus SDRAM DQM
From the SDRAM control machine. These pins select specific byte lanes of SDRAM
devices.
System Bus UPM Byte Select
From the UPM in the memory controller, these signals select specific byte lanes during
memory operations. The timing of these pins is programmed in the UPM. The actual driven
value depends on the address and size of the transaction and the port size of the
accessed device.
Host Read Data Strobe (In Asynchronous dual mode)
Used as a strobe for host read accesses.
Host Read/Write Select (in Asynchronous/Synchronous single mode)
Host read/write select.
Host Read Data Enable (In Synchronous dual mode)
Indicates valid data for host read accesses.
Host Burst
The host asserts this pin to indicate that the current transaction is a burst transaction in
synchronous mode only.
Host Data structure 0
Defines the data structure of the host access in DSI little-endian mode.
Host Data structure 1
Defines the data structure of the host access in DSI little-endian mode.
Host Chip Select
DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the
Chip_ID.
Host Broadcast Chip Select
DSI chip select for broadcast mode. Enables more than one DSI to share the same host
chip-select pin for broadcast write accesses.
Host Transfer Acknowledge
Upon a read access, indicates to the host when the data on the data bus is valid. Upon a
write access, indicates to the host that the data on the data bus was written to the DSI
write buffer.
Host Clock Input
Host clock signal for DSI synchronous mode.
Description