STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 11

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
3
The RIVA 128 is the first 128-bit 3D Multimedia
Accelerator to offer unparalleled 2D and 3D perfor-
mance, meeting all the requirements of the main-
stream PC graphics market and Microsoft’s
PC’97. The RIVA 128 introduces the most ad-
vanced Direct3D
delivers leadership VGA, 2D and Video perfor-
mance, enabling a range of applications from 3D
games through to DVD, Intercast
ferencing.
3.1
The RIVA 128 is designed to leverage existing PC
system resources such as system memory, high
bandwidth internal buses and bus master capabil-
ities. The synergy between the RIVA 128 graphics
pipeline architecture and that of the current gener-
ation PCI and next generation AGP platforms, de-
fines ground breaking performance levels at the
cost point currently required for mainstream PC
graphics solutions.
Execute versus DMA models
The RIVA 128 is architected to optimize PC sys-
tem resources in a manner consistent with the
AGP “Execute” model. In this model texture map
data for 3D applications is stored in system mem-
ory and individual texels are accessed as needed
by the graphics pipeline. This is a significant en-
hancement over the DMA model where entire tex-
ture maps are transferred into off-screen frame-
buffer memory.
The advantages of the Execute versus the DMA
model are:
To extend the advantages of the Execute model,
the RIVA 128’s proprietary texture cache and vir-
tual DMA bus master design overcomes the band-
width limitation of PCI, by sustaining a high texel
throughput with minimum bus utilization. The host
interface supports burst transactions up to 66MHz
and provides over 200MBytes/s on AGP. AGP ac-
Improved system performance since only the
required texels and not the entire texture map,
cross the bus.
Substantial cost savings since all the framebuff-
er is usable for the displayed screen and Z buff-
er and no part of it is required to be dedicated
to texture storage or texture caching.
There is no software overhead in the Direct3D
driver to manage texture caching between ap-
plication memory and the framebuffer.
OVERVIEW OF THE RIVA 128
BALANCED PC SYSTEM
acceleration solution and also
and video con-
cesses offer other performance enhancements
since they are from non-cacheable memory (no
snoop) and can be low priority to prevent proces-
sor stalls, or high priority to prevent graphics en-
gine stalls.
Building a balanced system
RIVA 128 is architected to provide the level of 3D
graphics performance and quality available in top
arcade platforms. To provide comparable scene
complexity in the 1997 time-frame, processors will
have to achieve new levels of floating point perfor-
mance. Profiles have shown that 1997 main-
stream CPUs will be able to transform over 1 mil-
lion lit, meshed triangles/s at 50% utilization using
Direct3D. This represents an order of magnitude
performance increase over anything attainable in
1996 PC games.
To build a balanced system the graphics pipeline
must match the CPU’s performance. It must be ca-
pable of rendering at least 1 million polygons/s in
order to avoid CPU stalls. Factors affecting this
system balance include:
3.2
The host interface boosts communication between
the host CPU and the RIVA 128. The optimized in-
terface performs burst DMA bus mastering for ef-
ficient and fast data transfer.
Direct3D compatibility. Minimizing the differ-
ences between the hardware interface and the
Direct3D data structures.
Triangle setup. Minimizing the number of for-
mat conversions and delta calculations done by
the CPU.
Display-list processing. Avoiding CPU stalls by
allowing the graphics pipeline to execute inde-
pendently of the CPU.
Vertex caching. Avoids saturating the host in-
terface with repeated vertices, lowering the traf-
fic on the bus and reducing system memory col-
lisions.
Host interface performance.
32-bit PCI version 2.1 or AGP version 1.0
Burst DMA Master and target
33MHz PCI clock rate or 66MHz AGP clock rate
Supports over 100MBytes/s with 33MHz PCI
and over 200MBytes/s on 66MHz AGP
Implements read buffer posting on AGP
Fully supports the “Execute” model on both PCI
and AGP
HOST INTERFACE
RIVA 128
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