STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 28

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA 128
6
The RIVA 128 SGRAM interface can be configured with a 2MByte 64-bit or 4MByte 128-bit data bus. With
a 128-bit bus, 4MBytes of SGRAM is supported as shown in Figure 22. All of the SGRAM signalling envi-
ronment is 3.3V.
Figure 22. 64-bit 2MByte and 128-bit 4MByte SGRAM configurations
Read and write accesses to SGRAM are burst oriented. SGRAM commands supported by the RIVA 128
are shown in Table 5. Initialization of the memory devices is performed in the standard SGRAM manner
as described in Section 6.1. Access sequences begin with an Active command followed by a Read or Write
command. The address bits registered coincident with the Read or Write command are used to select the
starting column location for the burst access. The RIVA 128 always uses a burst length of one and can
launch a new read or write on every cycle.
SGRAM has a fully synchronous interface with all signals registered on the positive edge of FBCLKx. Mul-
tiple clock outputs allow reductions in signal loading and more accuracy in data sampling at high frequen-
cy. The clock signals can be interspersed as shown in Figure 23, page 29 for optimal loading with either
2 or 4MBytes. The I/O timings relative to FBCLKx are shown in Figure 25, page 31.
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SGRAM FRAMEBUFFER INTERFACE
RIVA 128
FBD[63:32]
FBD[95:64]
FBD[127:96]
FBD[31:0]
256K
256K
256K
256K
x32
x32
x32
x32
128-BIT 3D MULTIMEDIA ACCELERATOR
Expansion to
4MBytes