STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 31

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
6.3
Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of SGRAM to give reduced
clock skew and loading. Additionally there is a clock feedback loop between FBCLK2 and FBCLKFB .
It is recommended that long traces are used without tunable components. If the layout includes provision
for expansion to 4MBytes, the clock path to the 2MByte parts should be at the end of the trace, and the
clock path to the 4MByte expansion located between the RIVA 128 and the 2MByte parts as shown in Fig-
ure 24. FBCLK2 and FBCLKFB should be shorted together as close to the package as possible and con-
nected via a 150
Figure 24. Recommended memory clock layout
6.4
Figure 25. SGRAM I/O timing diagram
Table 6. SGRAM I/O timing parameters
Symbol
t
t
CK
CH
LAYOUT OF FRAMEBUFFER CLOCK SIGNALS
SGRAM INTERFACE TIMING SPECIFICATION
FBA[9:0], FBD[63:0]
CLK period
CLK high time
FBD[63:0]
resistor to VCC (3.3V), again as close to the package as possible.
FBCLKx
Parameter
RIVA 128
FBCLKFB
FBCLK2
FBCLK0
FBCLK1
150
t
AS
-10
3.5
10
, t
t
LZ
t
DS
CH
t
Min.
AH
t
, t
AC
VDD (3.3V)
t
DH
CK
-12
4.5
to 4MBytes
12
Expansion
Bank 1
256K
256K
x32
x32
t
t
t
CL
-10
-
-
Max.
Bank 0
256K
256K
t
x32
x32
OH
-12
-
-
Unit
ns
ns
RIVA 128
Notes
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