STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 8

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA 128
2.3
2.4
8/77
Signal
Signal
Signal
MP_AD[7:0]
MPCLK
MPDTACK#
MPFRAME#
MPSTOP#
PCIGNT#
PCIINTA#
FBD[127:0]
FBA[10:0]
FBRAS#
FBCAS#
FBCS[1:0]#
FBWE#
FBDQM[15:0]
FBCLK0,
FBCLK1,
FBCLK2
FBCLKFB
FBCKE
SGRAM FRAMEBUFFER INTERFACE
VIDEO PORT
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
Description
Description
Description
Media Port 8-bit multiplexed address and data bus or ITU-R-656 video data bus when in
656 mode.
40MHz Media Port system clock or pixel clock when in 656 mode.
Media Port data transfer acknowledgment signal.
Initiates Media Port transfers when active, terminates transfers when inactive.
Media Port control signal used by the slave to terminate transfers.
Grant. This signal indicates to the RIVA 128 that access to the bus has been granted and
it can now become bus master.
When connected to AGP additional information is provided on AGPST[2:0] indicating that
the master is the recipient of previously requested read data (high or low priority), it is to
provide write data (high or low priority), for a previously enqueued write command or has
been given permission to start a bus transaction (AGP or PCI).
Interrupt request line. This open drain output is asserted and deasserted asynchronously
to PCICLK .
The 128-bit SGRAM memory data bus.
FBD[31:0] are also used to access up to 64KBytes of 8-bit ROM or Flash ROM, using
FBD[15:0] as address ROMA[15:0], FBD[31:24] as ROMD[7:0], FBD[17] as ROMWE#
and FBD[16] as ROMOE#.
Memory Address bus. Configuration strapping options are also decoded on these signals
during PCIRST# as described in Section 10, page 49. [FBA[10] is reserved for future
expansion and should be pulled to GND via a 4.7K resistor.
Memory Row Address Strobe for all memory devices.
Memory Column Address Strobe for all memory devices.
Memory Chip Select strobes for each SGRAM bank.
Memory Write Enable strobe for all memory devices.
Memory Data/Output Enable strobes for each of the 16 bytes.
Memory Clock signals. Separate clock signals FBCLK0 and FBCLK1 are provided for
each bank of SGRAM for reduced clock skew and loading. FBCLK2 is fed back to
FBCLKFB . Details of recommended memory clock layout are given in Section 6.3, page
31.
Framebuffer clock feedback. FBCLK2 is fed back to FBCLKFB .
This signal is currently a “no-connect” in this revision of the RIVA 128 but may be activated
to support the framebuffer memory clock enable for power management in future pin com-
patible devices. It is recommended that this pin is tied to VDD through a 4.7K pull-up
resistor.
128-BIT 3D MULTIMEDIA ACCELERATOR