STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 19

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 6. Single address - no delay by master
Figure 7 shows the RIVA 128 enqueuing 4 requests, where the first request is delayed by the maximum
2 cycles allowed. START is indicated on clock 2, but the RIVA 128 does not assert AGPPIPE# until clock
4. Note that PCIREQ# remains asserted on clock 6 to indicate that the current request is not the last one.
When PCIREQ# is deasserted on clock 7 with AGPPIPE# still asserted this indicates that the current ad-
dress is the last one to be enqueued during this transaction. AGPPIPE# must be deasserted on the next
clock when PCIREQ# is sampled as deasserted. If the RIVA 128 wants to enqueue more requests during
this bus operation, it continues asserting AGPPIPE# until all of its requests are enqueued or until it has
filled all the available request slots provided by the target.
Figure 7. Multiple addresses enqueued, maximum delay by RIVA 128
PCICBE[3:0]#
PCIAD[31:0]
AGPST[2:0]
AGPPIPE#
PCIREQ#
PCIGNT#
PCICLK
PCIAD[31:0]
AGPST[2:0]
AGPPIPE#
PCIREQ#
PCICBE#
PCIGNT#
PCICLK
1
xxx
xxx
1
111
2
111
2
A1
C1
111
3
111
3
xxx
4
111
A1
C1
4
xxx
xxx
A2
C2
5
5
xxx
A3
C3
xxx
6
6
A4
C4
xxx
xxx
7
7
xxx
RIVA 128
xxx
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