STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 45

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

STE10/100A
Table 8.
W* = only write when the transmit processor stopped.
W** = only write when the transmit and receive processor both stopped.
W*** = only write when the receive processor stopped.
11, 10
Bit #
9, 8
12
7
6
5
4
3
2
1
0
Control/status register description (continued)
Name
SBC
OM
MM
FC
PR
PB
SR
---
---
---
---
Force collision mode
0: disable
1: generate collision upon transmit (for testing in
loop-back mode)
Operating mode
00: normal
01: MAC loop-back, regardless of contents of
XLBEN (bit 14 of XR0, XCVR loop-back)
10,11: reserved
Reserved
Multicast mode
1: receive all multicast packets
Promiscuous mode
1: receive any good packet.
0: receive only the right destination address
packets
Stop back-off counter
1: back-off counter stops when carrier is active,
and resumes when carrier is dropped.
0: back-off counter is not effected by carrier
Reserved
Pass bad packet
1: receives any packets passing address filter,
including runt packets, CRC error, truncated
packets. For receiving all bad packets, PR (bit 6
of CSR6) should be set to 1.
0: filters all bad packets
Reserved
Start/stop receive
0: receive processor will enter stop state after
the current frame reception is completed. This
value is effective only when the receive
processor is in the running or suspending state.
Note: In “Stop Receive” state, the PAUSE packet
and remote wake up packet will not be affected
and can be received if the corresponding
function is enabled.
1: receive processor will enter running state.
Reserved
Description
Registers and descriptors description
Default
00
0
0
1
0
0
0
RW type
R/W***
R/W***
R/W***
R/W**
R/W**
R/W**
R/W
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