STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 53

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

STE10/100A
Table 8.
CSR18 (offset = 88h), CR - Command register bit31 to bit16 automatically recall from EEPROM
22, 21
30-28
27-24
14~0
Bit #
16
15
31
23
20
4LEDmod
AUXCL
ANISE
Control/status register description (continued)
Name
D3CS
AAIE
e_on
RFS
---
---
Added normal interrupt summary enable.
1: adds the interrupts of bits 30 and 31 of
ACSR7 (CSR17) to the normal interrupt
summary (bit 16 of CSR5).
Added abnormal interrupt summary enable.
1: adds the interrupt of bits 27, 28, and 29 of
ACSR7 (CSR17) to the abnormal interrupt
summary (bit 16 of CSR5).
These bits are the same as the interrupt enable
register of CSR7, and are accessible through
either CSR7 or CSR16.
D3cold power state wake up support. If this bit is
reset then bit 31 of PMR0 will be reset to ‘0’. If
this bit is asserted and an auxiliary power source
is detected then bit 31 of PMR0 will be set to ‘1’.
Aux. current load. These three bits report the
maximum 3.3Vaux current requirements for
STE10/100A chip. If bit 31 of PMR0 is ‘1’, the
default value is 111b, which means the
STE10/100A need 375 mA to support remote
wake-up in D3cold power state. Otherwise, the
default value is 000b, which means the
STE10/100A does not support remote wake-up
from D3cold power state.
Reserved
This bit is used to control the LED mode
selection.
If this bit is reset, mode 1 (3 LEDs) is selected;
the LEDs definition is:
- 100/10 speed
- Link/activity
- Full duplex/collision
If this bit is set, mode 2 (4 LEDs) is selected; the
LEDs definition is:
- 100 link
- 10 link
- Activity
- Full duplex/collision
Receive FIFO size control
11: 1K bytes
10: 2K bytes
01,00: reserved
Reserved
Description
Registers and descriptors description
EEPROM
EEPROM
EEPROM
EEPROM
Default
000b
from
from
from
from
10
0
0
0
0
RW type
R/W
R/W
R/W
R/W
R/W
R/W
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