STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 49

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

STE10/100A
Table 8.
R/W1C*, Read only and write one cleared.
CSR14 (offset = 70h), WPDR – Wake-up pattern data register
Offset
Bit #
7-3
9
8
2
1
0
0000h
0004h
0008h
000ch
0010h
0014h
0018h
001ch
0020h
31
Control/status register description (continued)
MPRE
Name
LSCE
WFR
MPR
LSC
---
Magic packet received enable. The STE10/100A
will include the “Magic Packet Received” event in
its set of wake-up events. If this bit is set,
STE10/100A will assert PMEST bit of PMR1
(CR49) after STE10/100A has received a Magic
packet.
Link status changed enable. The STE10/100A
will include the “Link status changed” event in its
set of wake-up events. If this bit is set,
STE10/100A will assert PMEST bit of PMR1
after STE10/100A has detected a link status
changed event.
Reserved
Wake-up frame received,
1: Indicates STE10/100A has received a wake-
up frame. It is cleared by writing a 1 or upon
power-up reset. It is not affected by a hardware
or software reset.
Magic packet received,
1: Indicates STE10/100A has received a magic
packet. It is cleared by writing a 1 or upon power-
up reset. It is not affected by a hardware or
software reset.
Link status changed,
1: Indicates STE10/100A has detected a link
status change event. It is cleared by writing a 1
or upon power-up reset. It is not affected by a
hardware or software reset.
CRC16 of pattern 1
Description
Wake-up pattern 1 mask bits 127:96
Wake-up pattern 2 mask bits 127:96
Wake-up pattern 1 mask bits 63:32
Wake-up pattern 1 mask bits 95:64
Wake-up pattern 2 mask bits 63:32
Wake-up pattern 2 mask bits 95:64
Wake-up pattern 1 mask bits 31:0
Wake-up pattern 2 mask bits 31:0
16 15
Registers and descriptors description
8
7
Default 1 if PM
& WOL bits of
both enabled.
CSR 18 are
Reserved
Default
X
X
X
0
0
pattern 1
RW type
Wake-up
R/W1C*
R/W1C*
R/W1C*
offset
R/W
R/W
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