STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 59

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

STE10/100A
Table 10.
XR0(offset = b4h) - XCR, XCVR control register. The default value is chosen as listed below.
R/W = Read/Write able. RO = Read only.
XR1(offset = b8h) - XSR, XCVR status register. All the bits of this register are read only.
Bit #
6~0
15
14
13
12
11
10
15
14
13
9
8
7
COLEN
XLBEN
SPSEL
DPSEL
Transceiver registers description
ANEN
PDEN
RSAN
Name
XRST
TXHD
TXFD
T4
---
---
Transceiver reset control.
1: reset transceiver. This bit will be cleared by
STE10/100A after transceiver reset has
completed.
Transceiver loop-back mode select.
1: transceiver loop-back mode is selected. OM
(CSR6 bits 11,10) of must contain 00.
Network speed select. This bit will be ignored if
Auto-negotiation is enabled (ANEN, XR0 bit 12).
1:100Mbps is selected.
0:10Mbps is selected.
Auto-negotiation ability control.
1: Auto-negotiation function is enabled.
0: Auto-negotiation is disabled.
Power down mode control.
1: transceiver power-down mode is selected. In
this mode, the STE10/100A transceivers are
turned off.
reserved
Re-start auto-negotiation process control.
1: Auto-negotiation process will be restarted.
This bit will be cleared by STE10/100A after the
Auto-negotiation has restarted.
Full/half duplex mode select.
1: full duplex mode is selected. This bit will be
ignored if auto-negotiation is enabled (ANEN,
XR0 bit 12).
Collision test control.
1: collision test is enabled.
Reserved
100BASE-T4 ability.
Always 0, since STE10/100A has no T4 ability.
100BASE-TX full duplex ability.
Always 1, since STE10/100A has 100BASE-TX
full duplex ability.
100BASE-TX half duplex ability.
Always 1, since STE10/100A has 100BASE-TX
half duplex ability.
Description
Registers and descriptors description
Default
0
0
1
1
0
0
0
0
0
0
0
1
1
RW type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
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