STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 48

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

Registers and descriptors description
48/82
Table 8.
CSR11 (offset = 58h), TMR - General - Purpose timer
CSR13 (offset = 68h), WCSR – Wake-up control/status register
31~17
24-18
15-11
15~0
Bit #
16
31
30
29
28
27
26
25
17
16
10
1
0
LinkOFF
LinkON
Control/status register description (continued)
WFRE
CRCT
WP1E
WP2E
WP3E
WP4E
WP5E
Name
SCLK
COM
SCS
GTV
---
---
---
---
Serial EEPROM clock.
High/Low this bit to provide the clock signal for
EEPROM.
Serial EEPROM chip select.
1: selects the serial EEPROM chip.
Reserved
Continuous operation mode.
1: sets the general-purpose timer in continuous
operating mode.
General-purpose timer value.
Sets the counter value. This is a count-down
counter with a cycle time of 204us.
Reserved
CRC-16 type
0: Initial contents = 0000h
1: Initial contents = FFFFh
Wake-up pattern one matched enable
Wake-up pattern two matched enable
Wake-up pattern three matched enable
Wake-up pattern four matched enable
Wake-up pattern five matched enable
Reserved
Link off detect enable. The STE10/100A will set
the LSC bit of CSR13 after it has detected that
link status has switched from ON to OFF.
Link on detect enable. The STE10/100A will set
the LSC bit of CSR13 after it has detected that
link status has switched from OFF to ON.
Reserved
Wake-up frame received enable. The
STE10/100A will include the “Wake-up Frame
Received” event in its set of wake-up events. If
this bit is set, STE10/100A will assert PMEST bit
of PMR1 (CR49) after STE10/100A has received
a matched wake-up frame.
Description
Default
1
1
0
0
0
0
0
0
0
0
0
0
0
STE10/100A
RW type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W