STE100A ST Microelectronics, Inc., STE100A Datasheet - Page 55

• Manufacturer Part Number: STE100A
• Description: PCI 10/100 Ethernet Controller with Integrated PHY (3.3v)
• Manufacturer: ST Microelectronics, Inc.

STE10/100A
Table 8.
CSR19 (offset = 8ch), PCIC - PCI bus performance counter
RO* = Read only and cleared by reading.
CSR20 (offset = 90h), PMCSR - Power management command and status
(The same register value mapping to CR49-PMR1)
31~16
31~16
14,13
15~8
12~9
Bit #
7~0
7~2
15
8
CLKCNT
PME_En
DWCNT
DSCAL
Control/status register description (continued)
PMES
Name
DSEL
---
---
---
The number of PCI clocks from read request
asserted to access completed. This PCI clock
count is accumulated for all the read command
cycles from the last CSR19 read to the current
CSR19 read.
Reserved
The number of double words accessed by the
last bus master. This double word count is
accumulated for all bus master data transactions
from the last CSR19 read to the current CSR19
read.
Reserved
PME_Status. This bit is set whenever the
STE10/100A detects a wake-up event,
regardless of the state of the PME-En bit.
Writing a “1” to this bit will clear it, causing the
STE10/100A to deassert PME# (if so enabled).
Writing a “0” has no effect.
Data_Scale. Indicates the scaling factor to be
used when interpreting the value of the data
register. This field is required for any function
that implements the data register.
The STE10/100A does not support data register
and Data_Scale.
Data_Select. This four bit field is used to select
which data is to be reported through the data
register and Data_Scale field. This field is
required for any function that implements the
data register.
The STE10/100A does not support Data_select.
PME_En. When set, enables the STE10/100A to
assert PME#. When cleared, disables the PME#
assertion.
Reserved
Description
Registers and descriptors description
000000b
Default
0000b
00b
0
0
0
0
RW type
RO*
RO*
RO
RO
RO
RO
RO
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