USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 27

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

MCU ISA Interface Registers
Note:
Note**: The “Inhibit” function is not valid for Memory-to-Memory DMA cycles
SMSC DS – USB97C100
BIT
HLDA Example: When the 8051 is running at 24MHz, and the 8237 is running at 2MHz, the 8237 may take
up to 1.5us to complete a transfer after deasserting HLDA . When running the 8051 at 24MHz, wait states
must be added when the 8237 is running at 2 or 4 MHz. When running the 8051 at 12MHz, wait states must
be added when the 8237 is running at 2 MHz.
7
6
5
4
3
2
1
0
(0x7F70 – RESET=0x00)
RESET_8237
INH_TC3
INH_TC2
INH_TC1
INH_TC0
BUS_REQ
NAME
HREQ
HLDA
AEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Table 33 – ISA Bus Request Register
This bit inhibits DMA channel 3 TC.**See Note Below
0 = TC is driven onto the ISA bus via EOP as before.
1 = TC is forced inactive.
This bit inhibits DMA channel 2 TC.** See Note Below
0 = TC is driven onto the ISA bus via EOP as before.
1 = TC is forced inactive.
This bit inhibits DMA channel 1 TC.** See Note Below
0 = TC is driven onto the ISA bus via EOP as before.
1 = TC is forced inactive.
This bit inhibits DMA channel 0 TC.** See Note Below
0 = TC is driven onto the ISA bus via EOP as before.
1 = TC is forced inactive.
'0' releases it for normal operation. May be used for clock
switching or power management functions.
This bit reflects the status of the 8237's AEN pin. This bit does
not generate an interrupt
The 8051 can grant the bus when it is ready via HLDA. This
should tri-state any common signals between the 8051 and the
8237 on the ISA bus.
This bit reflects the status of the 8237's HREQ bus request pin.
This bit does not generate an interrupt.
Writing a '1' holds the 8237 hardware reset input active. Writing
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ISA BUS REQUEST REGISTER
DESCRIPTION
Rev. 01/03/2001