USB97C100 Standard Microsystems Corporation, USB97C100 Datasheet - Page 36

• Manufacturer Part Number: USB97C100
• Description: USB97C100 Multi-endpoint Usb Peripheral Controller(not Recommended For Designs)
• Manufacturer: Standard Microsystems Corporation

SMSC DS – USB97C100
[7:0]
[7:0]
[7:0]
[7:4]
BIT
BIT
BIT
BIT
3
2
1
0
CLR_MASK: (ISA 0x000E)
MSTR_CLR: (ISA 0x000D)
TEMP_BYTE
SW_RESET
CH3_MASK
CH2_MASK
CH1_MASK
CH0_MASK
(ISA 0x000D)
(ISA 0x000F)
CLR_ALL
Reserved
ALL_MASK
RD_TEMP
NAME
NAME
NAME
NAME
Table 58 - Clear All Mask Bits Register
R/W
R/W
R/W
R/W
Table 55 - Read Temporary Register
W
W
W
W
W
W
W
R
Table 56 - Master Clear Register
Table 57 - Clear Mask Register
This location holds the value of the last byte transferred in a
memory-to-memory operation.
Writing to this register has the same effect on the registers
as a hardware reset. The 8237 will enter the idle state.
Writing to this register clears the mask bits of all four
channels and allows them to receive DMA requests.
Reserved
Channel 3 Mask Bit (1 = Set Mask, 0 = Clear Mask)
Channel 2 Mask Bit (1 = Set Mask, 0 = Clear Mask)
Channel 1 Mask Bit (1 = Set Mask, 0 = Clear Mask)
Channel 0 Mask Bit (1 = Set Mask, 0 = Clear Mask)
Page 36
WRITE ALL MASK BITS REGISTER
READ TEMPORARY REGISTER
MASTER CLEAR REGISTER
CLEAR MASK REGISTER
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Rev. 01/03/2001